adding reset logic to PLL control signals

54245d3c · Peter Jansweijer · ddf1a1e7 · 54245d3c
Commit 54245d3c authored Jan 24, 2020 by Peter Jansweijer
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Showing with 6 additions and 3 deletions

wrc_periph.vhd modules/wrc_core/wrc_periph.vhd +6 -3

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--- a/modules/wrc_core/wrc_periph.vhd
+++ b/modules/wrc_core/wrc_periph.vhd
@@ -552,10 +552,13 @@ begin
       pad_mosi_o           => pll_mosi_o,
       pad_miso_i           => pll_miso_i);

-   process(clk_sys_i)
+   process(clk_sys_i, rst_n_i)
   begin
-     if rising_edge(clk_sys_i) then
-
+     if (rst_n_i = '0') then
+       pll_reset_n_o <= '0';
+	   pll_clk_sel_o <= '0';
+	   pll_wr_mode_o <= (others => '0');
+	 elsif rising_edge(clk_sys_i) then
       if(sysc_regs_o.gpsr_pll_reset_o = '1') then
         pll_reset_n_o <= '0';
       elsif(sysc_regs_o.gpcr_pll_reset_o = '1') then