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White Rabbit core collection
Commit ddf1a1e7 authored by Peter Jansweijer's avatar Peter Jansweijer
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SPEC7 v2 modifications to ref design and WRITE top designs. 

WRITE design clk_10m_p/n_i input is ibufds plus add XDC property for non-clock capable pins.
parent 04fd6b13
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Showing with 68 additions and 34 deletions
board/spec7/xwrc_board_spec7.vhd
View file @ ddf1a1e7
......@@ -355,8 +355,9 @@ begin -- architecture struct
ext_ref_mul_stopped_o => ext_ref_mul_stopped,
ext_ref_rst_i => ext_ref_rst);
-- The PLL on the SPEC7 needs to be initialized before it outputs
-- clk_125m_gtx_p/n_i (which is
-- The PLL on the SPEC7 needs to be initialized before it outputs clk_125m_gtx_p/n_i.
-- Avoid a deadlock. The clk_dmtd is always present and is first used to bring alive
-- the LM32 that exectutes a PLL initialisation before switching to clk_pll_62m5.
cmp_bufgmux: BUFGMUX
port map (
......
top/spec7_ref_design/spec7_wr_ref_top.vhd
View file @ ddf1a1e7
......@@ -94,7 +94,7 @@ entity spec7_wr_ref_top is
dac_dmtd_din_o : out std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-- PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
......@@ -103,9 +103,8 @@ entity spec7_wr_ref_top is
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
pll_wr_mode_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- SFP I/O for transceiver
......@@ -323,9 +322,9 @@ begin -- architecture top
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_reset_n_o => open,
pll_lock_i => pll_lock_i,
pll_wr_mode_o => pll_wr_mode_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
......
top/spec7_ref_design/spec7_wr_ref_top.xdc
View file @ ddf1a1e7
......@@ -65,12 +65,12 @@ set_property PACKAGE_PIN D10 [get_ports dac_refclk_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_cs_n_o]
# -------------------------------------------------------------------------------
# -- AD9516 PLL Control signals
# -- PLL Control signals
# -------------------------------------------------------------------------------
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN B11 [get_ports pll_status_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_status_i]
set_property PACKAGE_PIN B12 [get_ports pll_mosi_o]
set_property PACKAGE_PIN C14 [get_ports pll_mosi_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_mosi_o]
set_property PACKAGE_PIN C11 [get_ports pll_miso_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_miso_i]
......@@ -80,12 +80,12 @@ set_property PACKAGE_PIN A14 [get_ports pll_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_cs_n_o]
set_property PACKAGE_PIN B14 [get_ports pll_sync_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_sync_n_o]
set_property PACKAGE_PIN C12 [get_ports pll_reset_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_reset_n_o]
set_property PACKAGE_PIN C14 [get_ports pll_refsel_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_refsel_o]
set_property PACKAGE_PIN A12 [get_ports pll_lock_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_lock_i]
set_property PACKAGE_PIN B12 [get_ports {pll_wr_mode_o[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[0]}]
set_property PACKAGE_PIN C12 [get_ports {pll_wr_mode_o[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[1]}]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
......@@ -271,10 +271,10 @@ set_property IOSTANDARD LVDS [get_ports abscal_txts_n_o]
# 10MHZ_IN
# Bulls-Eye B03, B04
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN J14 [get_ports clk_10m_p_i]
#set_property PACKAGE_PIN AF24 [get_ports clk_10m_p_i]
#set_property IOSTANDARD LVDS [get_ports clk_10m_p_i]
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN H14 [get_ports clk_10m_n_i]
#set_property PACKAGE_PIN AF25 [get_ports clk_10m_n_i]
#set_property IOSTANDARD LVDS [get_ports clk_10m_n_i]
# Reference Clock In (Bank 111)
......@@ -287,6 +287,20 @@ set_property IOSTANDARD LVDS [get_ports abscal_txts_n_o]
#set_property PACKAGE_PIN T4 [get_ports BE_RXP]
#set_property PACKAGE_PIN T3 [get_ports BE_RXN]
# CLK_DMTD In (Debug purposes only)
# Bulls-Eye B09, B10
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN J14 [get_ports clk_dmtd_p_i]
#set_property IOSTANDARD LVDS [get_ports clk_dmtd_p_i]
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN H14 [get_ports clk_dmtd_n_i]
#set_property IOSTANDARD LVDS [get_ports clk_dmtd_n_i]
# Bank 13 (HR) VCCO - 2.5 V
# Bulls-Eye B11 (PPS Single Ended)
#set_property PACKAGE_PIN AE23 [get_ports pps_i]
#set_property IOSTANDARD LVCMOS25 [get_ports pps_i]
# ---------------------------------------------------------------------------
# -- Digital I/O FMC Pins
# -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
......
top/spec7_write_design/spec7_write_top.vhd
View file @ ddf1a1e7
......@@ -153,22 +153,25 @@ entity spec7_write_top is
------------------------------------------------------------------------------
-- Digital I/O Bulls-Eye connections
------------------------------------------------------------------------------
-- 3, 4 ABSCAL_TXTS (Bank 35 C17,C16)
-- A09,A10 ABSCAL_TXTS (Bank 35 C17,C16)
abscal_txts_p_o : out std_logic;
abscal_txts_n_o : out std_logic;
-- 5, 6 PPS_OUT (Bank 35 G16,G15)
-- A01,A02 PPS_OUT (Bank 35 G16,G15)
pps_p_o : out std_logic;
pps_n_o : out std_logic;
-- 7, 8 PPS_IN (Bank 35 G14,F14)
-- B01,B02 PPS_IN (Bank 35 G14,F14)
pps_p_i : in std_logic;
pps_n_i : in std_logic;
-- 9,10 10MHz_out (Bank 35 F15,E15)
-- A03,A04 10MHz_out (Bank 35 F15,E15)
clk_10m_p_o : out std_logic;
clk_10m_n_o : out std_logic;
-- 11,12 10MHZ_in (Bank 35 J14,H14)
-- B03,B04 10MHZ_in (Bank 13 AF24,AF25)
clk_10m_p_i : in std_logic;
clk_10m_n_i : in std_logic;
-- B11 Single ended PPS_IN (Bank 13 AE23)
pps_i : in std_logic;
-- blink 1-PPS.
led_pps : out std_logic;
......@@ -402,7 +405,7 @@ begin -- architecture top
O => clk_10m_p_o,
OB => clk_10m_n_o);
cmp_ibufgds_10mhz_in: IBUFGDS
cmp_ibufds_10mhz_in: IBUFDS
generic map (
DIFF_TERM => true)
port map (
......
top/spec7_write_design/spec7_write_top.xdc
View file @ ddf1a1e7
......@@ -72,7 +72,7 @@ set_property PACKAGE_PIN D10 [get_ports dac_refclk_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_cs_n_o]
# -------------------------------------------------------------------------------
# -- AD9516 PLL Control signals
# -- PLL Control signals
# -------------------------------------------------------------------------------
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN B11 [get_ports pll_status_i]
......@@ -89,10 +89,10 @@ set_property PACKAGE_PIN B14 [get_ports pll_sync_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_sync_n_o]
set_property PACKAGE_PIN A12 [get_ports pll_lock_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_lock_i]
set_property PACKAGE_PIN B12 [get_ports pll_wr_mode_o_0]]
set_property IOSTANDARD LVCMOS18 [get_ports pll_wr_mode_o_0]
set_property PACKAGE_PIN C12 [get_ports pll_wr_mode_o_1]
set_property IOSTANDARD LVCMOS18 [get_ports pll_wr_mode_o_1]
set_property PACKAGE_PIN B12 [get_ports {pll_wr_mode_o[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[0]}]
set_property PACKAGE_PIN C12 [get_ports {pll_wr_mode_o[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[1]}]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
......@@ -241,7 +241,7 @@ set_property PACKAGE_PIN E15 [get_ports clk_10m_n_o]
set_property IOSTANDARD LVDS [get_ports clk_10m_n_o]
# 125MHz Reference Clock Out
# Bulls-Eye A05, A06 (connected to AD9516)
# Bulls-Eye A05, A06 (connected to LTC6950)
# TX Spare GTX Out (Bank 112 GTX3)
# Bulls-Eye A07, A08
......@@ -276,13 +276,16 @@ set_property PACKAGE_PIN F14 [get_ports pps_n_i]
set_property IOSTANDARD LVDS [get_ports pps_n_i]
# 10MHZ_in
# Bulls-Eye B03, B04
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN J14 [get_ports clk_10m_p_i]
set_property IOSTANDARD LVDS [get_ports clk_10m_p_i]
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN H14 [get_ports clk_10m_n_i]
set_property IOSTANDARD LVDS [get_ports clk_10m_n_i]
# Bulls-Eye B03, B04 (via LTC6957)
# Bank 13 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN AF24 [get_ports clk_10m_p_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_10m_p_i]
# Bank 13 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN AF25 [get_ports clk_10m_n_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_10m_n_i]
# Signal clk_ext_10m is soly used for sampling the phase relation w.r.t. refclock.
# The signals clk_10m_p/n_i are routed to a non-clock capable pins. Hence:
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ext_10m]
# Reference Clock In (Bank 111)
# Bulls-Eye B05, B06
......@@ -294,6 +297,20 @@ set_property IOSTANDARD LVDS [get_ports clk_10m_n_i]
#set_property PACKAGE_PIN T4 [get_ports BE_RXP]
#set_property PACKAGE_PIN T3 [get_ports BE_RXN]
# Spare CLK_DMTD In
# Bulls-Eye B09, B10
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN J14 [get_ports clk_dmtd_p_i]
#set_property IOSTANDARD LVDS [get_ports clk_dmtd_p_i]
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN H14 [get_ports clk_dmtd_n_i]
#set_property IOSTANDARD LVDS [get_ports clk_dmtd_n_i]
# Bank 13 (HR) VCCO - 2.5 V
# Bulls-Eye B11 (PPS Single Ended)
set_property PACKAGE_PIN AE23 [get_ports pps_i]
set_property IOSTANDARD LVCMOS25 [get_ports pps_i]
# ---------------------------------------------------------------------------
# -- FMC connector
......
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