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White Rabbit core collection
Commit 300b0560 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrcore_v2: importing the newest wr_mini_nic (from wishbonized branch)

parent b3bfa66d
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Showing with 244 additions and 115 deletions
modules/wr_mini_nic/mini_nic.wb
View file @ 300b0560
......@@ -199,8 +199,30 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "Memory protection reg";
prefix = "MPROT";
field {
name = "address range lo";
size = 16;
prefix = "LO";
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "address range hi";
size = 16;
prefix = "HI";
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
irq {
name = "TX DMA interrupt";
......
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ 300b0560
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Mon Oct 24 18:21:19 2011
-- Created : Sun Nov 6 00:30:17 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -49,6 +49,8 @@ signal minic_mcr_tx_start_dly0 : std_logic ;
signal minic_mcr_tx_start_int : std_logic ;
signal minic_mcr_rx_en_int : std_logic ;
signal minic_mcr_rx_class_int : std_logic_vector(7 downto 0);
signal minic_mprot_lo_int : std_logic_vector(15 downto 0);
signal minic_mprot_hi_int : std_logic_vector(15 downto 0);
signal eic_idr_int : std_logic_vector(2 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(2 downto 0);
......@@ -95,6 +97,8 @@ begin
regs_o.rx_addr_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
tx_ts_read_ack_o <= '0';
minic_mprot_lo_int <= "0000000000000000";
minic_mprot_hi_int <= "0000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -253,6 +257,16 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
minic_mprot_lo_int <= wrdata_reg(15 downto 0);
minic_mprot_hi_int <= wrdata_reg(31 downto 16);
else
rddata_reg(15 downto 0) <= minic_mprot_lo_int;
rddata_reg(31 downto 16) <= minic_mprot_hi_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
......@@ -450,6 +464,10 @@ begin
-- Timestamp value
-- interrupt counter
-- status of wb_irq_o line
-- address range lo
regs_o.mprot_lo_o <= minic_mprot_lo_int;
-- address range hi
regs_o.mprot_hi_o <= minic_mprot_hi_int;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
......
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @ 300b0560
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Mon Oct 24 18:21:19 2011
-- Created : Sun Nov 6 00:30:17 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -64,6 +64,8 @@ package minic_wbgen2_pkg is
rx_addr_load_o : std_logic;
rx_avail_o : std_logic_vector(23 downto 0);
rx_avail_load_o : std_logic;
mprot_lo_o : std_logic_vector(15 downto 0);
mprot_hi_o : std_logic_vector(15 downto 0);
end record;
constant c_minic_out_registers_init_value: t_minic_out_registers := (
......@@ -75,7 +77,9 @@ package minic_wbgen2_pkg is
rx_addr_o => (others => '0'),
rx_addr_load_o => '0',
rx_avail_o => (others => '0'),
rx_avail_load_o => '0'
rx_avail_load_o => '0',
mprot_lo_o => (others => '0'),
mprot_hi_o => (others => '0')
);
function "or" (left, right: t_minic_in_registers) return t_minic_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ 300b0560
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