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White Rabbit core collection
Commit 337b6b8b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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modules/wrc_core: added auxillary WB Master port

parent 7ce1657f
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Showing with 86 additions and 11 deletions
modules/wrc_core/wr_core.vhd
View file @ 337b6b8b
......@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2012-05-02
-- Last update: 2012-06-15
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -43,6 +43,8 @@
-- +0x400: Syscon
-- +0x500: UART
-- +0x600: OneWire
-- +0x700: Auxillary space (Etherbone config, etc)
library ieee;
use ieee.std_logic_1164.all;
......@@ -169,6 +171,19 @@ entity wr_core is
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------------------
-- Auxillary WB master
-----------------------------------------
aux_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_we_o : out std_logic;
aux_cyc_o : out std_logic;
aux_stb_o : out std_logic;
aux_ack_i : in std_logic := '1';
aux_stall_i : in std_logic := '0';
-----------------------------------------
-- External Fabric I/F
-----------------------------------------
......@@ -288,20 +303,23 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--WB Secondary Crossbar
-----------------------------------------------------------------------------
constant c_secbar_layout : t_sdb_record_array(6 downto 0) :=
constant c_secbar_layout : t_sdb_record_array(7 downto 0) :=
(0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
3 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00000300"),
4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"), -- Syscon
5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"), -- UART
6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600")); -- 1-Wire
6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"), -- 1-Wire
7 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000700") -- aux WB bus
);
constant c_secbar_sdb_address : t_wishbone_address := x"00000800";
constant c_secbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
signal secbar_master_i : t_wishbone_master_in_array(6 downto 0);
signal secbar_master_o : t_wishbone_master_out_array(6 downto 0);
signal secbar_master_i : t_wishbone_master_in_array(7 downto 0);
signal secbar_master_o : t_wishbone_master_out_array(7 downto 0);
-----------------------------------------------------------------------------
--WB intercon
......@@ -805,7 +823,7 @@ begin
WB_SECONDARY_CON : xwb_sdb_crossbar
generic map(
g_num_masters => 1,
g_num_slaves => 7,
g_num_slaves => 8,
g_registered => true,
g_wraparound => true,
g_layout => c_secbar_layout,
......@@ -838,6 +856,20 @@ begin
periph_slave_i(1) <= secbar_master_o(5);
periph_slave_i(2) <= secbar_master_o(6);
aux_adr_o <= secbar_master_o(7).adr;
aux_dat_o <= secbar_master_o(7).dat;
aux_sel_o <= secbar_master_o(7).sel;
aux_cyc_o <= secbar_master_o(7).cyc;
aux_stb_o <= secbar_master_o(7).stb;
aux_we_o <= secbar_master_o(7).we;
secbar_master_i(7).dat <= aux_dat_i;
secbar_master_i(7).ack <= aux_ack_i;
secbar_master_i(7).stall <= aux_stall_i;
secbar_master_i(7).err <= '0';
secbar_master_i(7).rty <= '0';
-----------------------------------------------------------------------------
-- WBP MUX
-----------------------------------------------------------------------------
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 337b6b8b
......@@ -155,6 +155,7 @@ package wrcore_pkg is
version => x"00000001",
date => x"20120305",
name => "WR-Periph-UART ")));
constant c_wrc_periph2_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
......@@ -170,6 +171,24 @@ package wrcore_pkg is
version => x"00000001",
date => x"20120305",
name => "WR-Periph-1Wire ")));
constant c_wrc_periph3_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"779c5445",
version => x"00000001",
date => x"20120615",
name => "WR-Periph-AuxWB ")));
component wrc_periph is
generic(
g_phys_uart : boolean := true;
......
modules/wrc_core/xwr_core.vhd
View file @ 337b6b8b
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2012-04-25
-- Last update: 2012-06-15
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -140,9 +140,12 @@ entity xwr_core is
-----------------------------------------
--External WB interface
-----------------------------------------
slave_i : in t_wishbone_slave_in;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
-----------------------------------------
-- External Fabric I/F
-----------------------------------------
......@@ -161,7 +164,7 @@ entity xwr_core is
-- Timecode/Servo Control
-----------------------------------------
tm_link_up_o : out std_logic;
tm_link_up_o : out std_logic;
-- DAC Control
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
......@@ -257,6 +260,17 @@ architecture struct of xwr_core is
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
aux_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
aux_we_o : out std_logic := '0';
aux_cyc_o : out std_logic := '0';
aux_stb_o : out std_logic := '0';
aux_ack_i : in std_logic;
aux_stall_i : in std_logic;
ext_snk_adr_i : in std_logic_vector(1 downto 0) := "00";
ext_snk_dat_i : in std_logic_vector(15 downto 0) := x"0000";
ext_snk_sel_i : in std_logic_vector(1 downto 0) := "00";
......@@ -284,7 +298,7 @@ architecture struct of xwr_core is
txtsu_stb_o : out std_logic;
txtsu_ack_i : in std_logic;
tm_link_up_o : out std_logic;
tm_link_up_o : out std_logic;
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic;
......@@ -373,6 +387,16 @@ begin
wb_rty_o => slave_o.rty,
wb_stall_o => slave_o.stall,
aux_adr_o => aux_master_o.adr,
aux_dat_o => aux_master_o.dat,
aux_sel_o => aux_master_o.sel,
aux_cyc_o => aux_master_o.cyc,
aux_stb_o => aux_master_o.stb,
aux_we_o => aux_master_o.we,
aux_stall_i => aux_master_i.stall,
aux_ack_i => aux_master_i.ack,
aux_dat_i => aux_master_i.dat,
ext_snk_adr_i => wrf_snk_i.adr,
ext_snk_dat_i => wrf_snk_i.dat,
ext_snk_sel_i => wrf_snk_i.sel,
......@@ -400,7 +424,7 @@ begin
txtsu_stb_o => timestamps_o.stb,
txtsu_ack_i => timestamps_ack_i,
tm_link_up_o => tm_link_up_o,
tm_link_up_o => tm_link_up_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
......
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