wr_core: without reversing softpll dmtd inputs main pll locks much faster

35723911 · Grzegorz Daniluk · d783a467 · 35723911
Commit 35723911 authored Apr 13, 2012 by Grzegorz Daniluk
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wr_core.vhd modules/wrc_core/wr_core.vhd +1 -1

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--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -442,7 +442,7 @@ begin
  U_SOFTPLL : xwr_softpll_ng
    generic map(
      g_with_ext_clock_input => g_with_external_clock_input,
-      g_reverse_dmtds        => true,
+      g_reverse_dmtds        => false,
      g_with_undersampling   => false,
      g_with_period_detector => false,
      g_with_debug_fifo      => true,