Add generic parameter g_num_ports for WRPC.

Add extra MINIC/Endpoint in WRPC. Add a simple dualport switch module.

Add generic parameter g_num_ports for WRPC.
Add extra MINIC/Endpoint in WRPC. Add a simple dualport switch module.
3654cd97 · li hongming · 9a125269 · 3654cd97 · 3654cd97 · 3654cd97
Commit 3654cd97 authored Jan 23, 2019 by li hongming
11 changed files
--- a/board/common/wr_board_pkg.vhd
+++ b/board/common/wr_board_pkg.vhd
@@ -111,6 +111,7 @@ package wr_board_pkg is
      g_softpll_enable_debugger   : boolean                        := FALSE;
      g_vuart_fifo_size           : integer                        := 1024;
      g_pcs_16bit                 : boolean                        := FALSE;
+      g_num_ports                 : integer                        := 1;
      g_diag_id                   : integer                        := 0;
      g_diag_ver                  : integer                        := 0;
      g_diag_ro_size              : integer                        := 0;
@@ -210,7 +211,17 @@ package wr_board_pkg is
      pps_csync_o          : out std_logic;
      pps_p_o              : out std_logic;
      pps_led_o            : out std_logic;
-      link_ok_o            : out std_logic);
+      link_ok_o            : out std_logic;
+      dp_phy8_o            : out t_phy_8bits_from_wrc;
+      dp_phy8_i            : in  t_phy_8bits_to_wrc                               := c_dummy_phy8_to_wrc;
+      dp_phy16_o           : out t_phy_16bits_from_wrc;
+      dp_phy16_i           : in  t_phy_16bits_to_wrc                              := c_dummy_phy16_to_wrc;
+      dp_timestamps_o         : out t_txtsu_timestamp;
+      dp_timestamps_ack_i     : in  std_logic := '1';
+      dp_fc_tx_pause_req_i    : in  std_logic                     := '0';
+      dp_fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0) := x"0000";
+      dp_fc_tx_pause_ready_o  : out std_logic
+      );
  end component xwrc_board_common;

 end wr_board_pkg;

--- a/board/common/xwrc_board_common.vhd
+++ b/board/common/xwrc_board_common.vhd
@@ -66,6 +66,7 @@ entity xwrc_board_common is
    g_softpll_enable_debugger   : boolean                        := FALSE;
    g_vuart_fifo_size           : integer                        := 1024;
    g_pcs_16bit                 : boolean                        := FALSE;
+    g_num_ports                 : integer                        := 1;
    g_diag_id                   : integer                        := 0;
    g_diag_ver                  : integer                        := 0;
    g_diag_ro_size              : integer                        := 0;
@@ -261,7 +262,21 @@ entity xwrc_board_common is
    pps_p_o     : out std_logic;
    pps_led_o   : out std_logic;
    -- Link ok indication
-    link_ok_o : out std_logic
+    link_ok_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Another PHY I/f for dualport
+    ---------------------------------------------------------------------------
+    dp_phy8_o  : out t_phy_8bits_from_wrc;
+    dp_phy8_i  : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    dp_phy16_o : out t_phy_16bits_from_wrc;
+    dp_phy16_i : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+    
+    dp_timestamps_o         : out t_txtsu_timestamp;
+    dp_timestamps_ack_i     : in  std_logic := '1';
+    dp_fc_tx_pause_req_i    : in  std_logic                     := '0';
+    dp_fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0) := x"0000";
+    dp_fc_tx_pause_ready_o  : out std_logic
    );

 end entity xwrc_board_common;
@@ -381,6 +396,7 @@ begin  -- architecture struct
      g_softpll_enable_debugger   => g_softpll_enable_debugger,
      g_vuart_fifo_size           => g_vuart_fifo_size,
      g_pcs_16bit                 => g_pcs_16bit,
+      g_num_ports                 => g_num_ports,
      g_records_for_phy           => TRUE,
      g_diag_id                   => c_diag_id,
      g_diag_ver                  => c_diag_ver,
@@ -480,7 +496,35 @@ begin  -- architecture struct
      rst_aux_n_o          => aux_rst_n,
      aux_diag_i           => aux_diag_in,
      aux_diag_o           => aux_diag_out,
-      link_ok_o            => link_ok);
+      link_ok_o            => link_ok,
+      dp_phy8_o            => dp_phy8_o,
+      dp_phy8_i            => dp_phy8_i,
+      dp_phy16_o           => dp_phy16_o,
+      dp_phy16_i           => dp_phy16_i,
+      dp_phy_ref_clk_i     => '0',
+      dp_phy_tx_data_o     => open,
+      dp_phy_tx_k_o        => open,
+      dp_phy_tx_disparity_i=> '0',
+      dp_phy_tx_enc_err_i  => '0',
+      dp_phy_rx_data_i     => (others => '0'),
+      dp_phy_rx_rbclk_i    => '0',
+      dp_phy_rx_k_i        => (others => '0'),
+      dp_phy_rx_enc_err_i  => '0',
+      dp_phy_rx_bitslide_i => (others => '0'),
+      dp_phy_rst_o         => open,
+      dp_phy_rdy_i         => '1',
+      dp_phy_loopen_o      => open,
+      dp_phy_loopen_vec_o  => open,
+      dp_phy_tx_prbs_sel_o => open,
+      dp_phy_sfp_tx_fault_i=> '0',
+      dp_phy_sfp_los_i     => '0',
+      dp_phy_sfp_tx_disable_o => open,
+      dp_timestamps_o         => dp_timestamps_o,
+      dp_timestamps_ack_i     => dp_timestamps_ack_i,
+      dp_fc_tx_pause_req_i    => dp_fc_tx_pause_req_i,
+      dp_fc_tx_pause_delay_i  => dp_fc_tx_pause_delay_i,
+      dp_fc_tx_pause_ready_o  => dp_fc_tx_pause_ready_o
+      );

  link_ok_o       <= link_ok;
  tm_time_valid_o <= tm_time_valid;

--- a/board/cute/wr_cute_pkg.vhd
+++ b/board/cute/wr_cute_pkg.vhd
@@ -65,7 +65,9 @@ package wr_cute_pkg is
      g_sfp0_enable               : integer              := 1;
      g_sfp1_enable               : integer              := 0;
      g_phy_refclk_sel            : integer              := 0;
-      g_multiboot_enable          : boolean              := false);
+      g_multiboot_enable          : boolean              := false;
+      g_num_ports                 : integer              := 1
+      );
    port (
      areset_n_i          : in  std_logic;
      areset_edge_n_i     : in  std_logic := '1';

--- a/board/cute/xwrc_board_cute.vhd
+++ b/board/cute/xwrc_board_cute.vhd
@@ -83,7 +83,8 @@ entity xwrc_board_cute is
    g_sfp0_enable               : integer              := 1;
    g_sfp1_enable               : integer              := 0;
    g_phy_refclk_sel            : integer              := 0;
-    g_multiboot_enable          : boolean              := false
+    g_multiboot_enable          : boolean              := false;
+    g_num_ports                 : integer              := 1
    );
  port (
    ---------------------------------------------------------------------------
@@ -277,7 +278,13 @@ entity xwrc_board_cute is
    pps_led_o  : out std_logic;
    pps_csync_o: out std_logic;
    -- Link ok indication
-    link_ok_o  : out std_logic
+    link_ok_o  : out std_logic;
+
+    dp_timestamps_o     : out t_txtsu_timestamp;
+    dp_timestamps_ack_i : in  std_logic := '1';
+    dp_fc_tx_pause_req_i   : in  std_logic                     := '0';
+    dp_fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+    dp_fc_tx_pause_ready_o : out std_logic
    );

 end entity xwrc_board_cute;
@@ -402,6 +409,9 @@ architecture struct of xwrc_board_cute is
  signal sfp1_tx_disable_out  : std_logic;
  signal sfp1_los_in          : std_logic;

+  signal dp_phy8_to_wrc   : t_phy_8bits_to_wrc;
+  signal dp_phy8_from_wrc : t_phy_8bits_from_wrc;
+
  signal tm_time_valid : std_logic;

  -- ext 10M clock output
@@ -557,6 +567,30 @@ begin  -- architecture struct
    sfp1_tx_fault_in   <= sfp1_tx_fault_i;
    sfp1_los_in        <= sfp1_los_i;

+    dp_cmp_xwrc_platform : xwrc_platform_xilinx
+      generic map (
+        g_fpga_family               => "spartan6",
+        g_with_external_clock_input => false,
+        g_use_default_plls          => false,
+        g_gtp_enable_ch0            => 0,
+        g_gtp_enable_ch1            => 1,
+        g_phy_refclk_sel            => g_phy_refclk_sel,
+        g_simulation                => g_simulation)
+      port map (
+        areset_n_i            => areset_n_i,
+        clk_125m_gtp_p_i      => clk_125m_gtp1_p_i,
+        clk_125m_gtp_n_i      => clk_125m_gtp1_n_i,
+        clk_125m_ref_i        => clk_pll_125m,
+        sfp_txn_o             => sfp1_txn_out,
+        sfp_txp_o             => sfp1_txp_out,
+        sfp_rxn_i             => sfp1_rxn_in,
+        sfp_rxp_i             => sfp1_rxp_in,
+        sfp_tx_fault_i        => sfp1_tx_fault_in,
+        sfp_los_i             => sfp1_los_in,
+        sfp_tx_disable_o      => sfp1_tx_disable_out,
+        phy8_o                => dp_phy8_to_wrc,
+        phy8_i                => dp_phy8_from_wrc);
+
  end generate;

  sfp0_rate_select_o <= '1';
@@ -668,7 +702,8 @@ begin  -- architecture struct
      g_streamers_op_mode         => g_streamers_op_mode,
      g_tx_streamer_params        => g_tx_streamer_params,
      g_rx_streamer_params        => g_rx_streamer_params,
-      g_fabric_iface              => g_fabric_iface
+      g_fabric_iface              => g_fabric_iface,
+      g_num_ports                 => g_num_ports
      )
    port map (
      clk_sys_i            => clk_pll_62m5,
@@ -757,7 +792,15 @@ begin  -- architecture struct
      pps_p_o              => pps_p_o,
      pps_csync_o          => pps_csync,
      pps_led_o            => pps_led_o,
-      link_ok_o            => link_ok_o);
+      link_ok_o            => link_ok_o,
+      dp_phy8_o            => dp_phy8_from_wrc,
+      dp_phy8_i            => dp_phy8_to_wrc,
+      dp_timestamps_o         => dp_timestamps_o,
+      dp_timestamps_ack_i     => dp_timestamps_ack_i,
+      dp_fc_tx_pause_req_i    => dp_fc_tx_pause_req_i,
+      dp_fc_tx_pause_delay_i  => dp_fc_tx_pause_delay_i,
+      dp_fc_tx_pause_ready_o  => dp_fc_tx_pause_ready_o
+      );

  tm_time_valid_o <= tm_time_valid;
  pps_csync_o     <= pps_csync;

--- a/modules/fabric/wr_fabric_pkg.vhd
+++ b/modules/fabric/wr_fabric_pkg.vhd
@@ -187,7 +187,26 @@ package wr_fabric_pkg is
      bytesel_i : in  std_logic;
      dreq_o    : out std_logic);
  end component;
+  
+  component xwrf_dp_switch is
+    generic(
+      -- g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+      -- g_address_granularity   : t_wishbone_address_granularity := WORD;
+      g_num_ports       : integer := 2 );
+    port(
+      clk_sys_i         : in  std_logic;
+      rst_n_i           : in  std_logic;

+      -- wb_i              : in  t_wishbone_slave_in;
+      -- wb_o              : out t_wishbone_slave_out;
+
+      port_wrf_snk_i   : in  t_wrf_sink_in_array(g_num_ports-1 downto 0);
+      port_wrf_snk_o   : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
+      port_wrf_src_o   : out t_wrf_source_out_array(g_num_ports-1 downto 0);
+      port_wrf_src_i   : in  t_wrf_source_in_array(g_num_ports-1 downto 0)
+      );
+  end component;
+  
 end wr_fabric_pkg;

 package body wr_fabric_pkg is

--- a/modules/fabric/xwrf_dp_switch/Manifest.py
+++ b/modules/fabric/xwrf_dp_switch/Manifest.py
--- a/modules/fabric/xwrf_dp_switch/xwrf_dp_switch.vhd
+++ b/modules/fabric/xwrf_dp_switch/xwrf_dp_switch.vhd
+-------------------------------------------------------------------------------
+-- Title      : Simple dualport switch
+-- Project    :
+-------------------------------------------------------------------------------
+-- File       : xwrf_dp_switch.vhd
+-- Author     : lihm
+-- Company    : Tsinghua
+-- Created    : 2018-12-03
+-- Last update: 2018-12-03
+-- Platform   : Xilinx Spartan 6
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Simple dualport switch
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2018-11-3  1.0      lihm            Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wr_fabric_pkg.all;
+use work.wishbone_pkg.all;
+use work.genram_pkg.all;
+use work.endpoint_pkg.all;
+use work.endpoint_private_pkg.all;
+
+entity xwrf_dp_switch is
+  generic(
+    -- g_interface_mode        : t_wishbone_interface_mode      := CLASSIC;
+    -- g_address_granularity   : t_wishbone_address_granularity := WORD;
+    g_num_ports       : integer := 2 );
+  port(
+    clk_sys_i         : in  std_logic;
+    rst_n_i           : in  std_logic;
+
+    -- wb_i              : in  t_wishbone_slave_in;
+    -- wb_o              : out t_wishbone_slave_out;
+
+    port_wrf_snk_i   : in  t_wrf_sink_in_array(g_num_ports-1 downto 0);
+    port_wrf_snk_o   : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
+    port_wrf_src_o   : out t_wrf_source_out_array(g_num_ports-1 downto 0);
+    port_wrf_src_i   : in  t_wrf_source_in_array(g_num_ports-1 downto 0)
+    );
+end xwrf_dp_switch;
+
+architecture behav of xwrf_dp_switch is
+   
+  -- signal wb_out : t_wishbone_slave_out;
+  -- signal wb_in  : t_wishbone_slave_in;
+  -- signal regs_fromwb  : t_dp_switch_out_registers;
+  -- signal regs_towb    : t_dp_switch_in_registers;
+
+  type t_dp_switch_rxfsm is (IDLE, PAYLOAD, DROP, FEND);
+  type t_dp_switch_rxfsm_array is array (natural range <>) of t_dp_switch_rxfsm;
+  signal port_rxfsm : t_dp_switch_rxfsm_array(g_num_ports-1 downto 0);
+  type t_dp_switch_txfsm is (IDLE, GET_SIZE, STATUS ,PAYLOAD, EOF);
+  type t_dp_switch_txfsm_array is array (natural range <>) of t_dp_switch_txfsm;
+  signal port_txfsm : t_dp_switch_txfsm_array(g_num_ports-1 downto 0);
+
+  signal port_fword_valid : std_logic_vector(g_num_ports-1 downto 0);
+
+  signal port_ffifo_wr   : std_logic_vector(g_num_ports-1 downto 0);
+  signal port_ffifo_rd   : std_logic_vector(g_num_ports-1 downto 0);
+  signal port_ffifo_full : std_logic_vector(g_num_ports-1 downto 0);
+  type t_frame_fifo_array is array (natural range <>) of std_logic_vector(15 downto 0);
+  signal port_ffifo_in : t_frame_fifo_array(g_num_ports-1 downto 0);
+  signal port_ffifo_out : t_frame_fifo_array(g_num_ports-1 downto 0);
+
+  type t_frame_size_array is array (natural range <>) of unsigned(15 downto 0);
+  signal port_fsize    : t_frame_size_array(g_num_ports-1 downto 0);
+  signal port_txsize   : t_frame_size_array(g_num_ports-1 downto 0);
+
+  signal port_sfifo_wr    : std_logic_vector(g_num_ports-1 downto 0);
+  signal port_sfifo_rd    : std_logic_vector(g_num_ports-1 downto 0);
+  signal port_sfifo_empty : std_logic_vector(g_num_ports-1 downto 0);
+  signal port_sfifo_full  : std_logic_vector(g_num_ports-1 downto 0);
+  type t_size_fifo_array is array (natural range <>) of std_logic_vector(15 downto 0);
+  signal port_sfifo_in  : t_size_fifo_array(g_num_ports-1 downto 0);
+  signal port_sfifo_out : t_size_fifo_array(g_num_ports-1 downto 0);
+  
+  signal port_src_fab  : t_fab_pipe(g_num_ports-1 downto 0);
+  signal port_src_dreq : std_logic_vector(g_num_ports-1 downto 0);
+
+  constant stored_status : t_wrf_status_reg :=
+    ('0', '1', '1', '0', '0', (others => '0')); -- has_smac, has_crc
+
+begin
+
+  -------------------------------------------
+  --  Standard Wishbone stuff
+  -------------------------------------------
+  -- U_Slave_adapter : wb_slave_adapter
+  --   generic map (
+  --     g_master_use_struct  => true,
+  --     g_master_mode        => CLASSIC,
+  --     g_master_granularity => WORD,
+  --     g_slave_use_struct   => true,
+  --     g_slave_mode         => g_interface_mode,
+  --     g_slave_granularity  => g_address_granularity)
+  --   port map (
+  --     clk_sys_i  => clk_sys_i,
+  --     rst_n_i    => rst_n_i,
+  --     slave_i    => wb_i,
+  --     slave_o    => wb_o,
+  --     master_i   => wb_out,
+  --     master_o   => wb_in
+  --     );
+
+  -- U_WB_SLAVE: dualport_wishbone_controller
+  --   port map(
+  --     rst_n_i    => rst_n_i,
+  --     clk_sys_i  => clk_sys_i,
+  --     wb_adr_i   => wb_in.adr(2 downto 0),
+  --     wb_dat_i   => wb_in.dat,
+  --     wb_dat_o   => wb_out.dat,
+  --     wb_cyc_i   => wb_in.cyc,
+  --     wb_sel_i   => wb_in.sel,
+  --     wb_stb_i   => wb_in.stb,
+  --     wb_we_i    => wb_in.we,
+  --     wb_ack_o   => wb_out.ack,
+  --     wb_stall_o => wb_out.stall,
+  --     regs_i     => regs_towb,
+  --     regs_o     => regs_fromwb);
+
+  -- wb_out.rty <= '0';
+  -- wb_out.err <= '0';
+  -- wb_out.int <= '0';
+
+--------------------------------------------------------------------------------------
+--- Dual port Data Switch Part --
+--------------------------------------------------------------------------------------    
+  -------------------------------------------
+  -- FIFO
+  -------------------------------------------
+  gen_fifo : for i in 0 to g_num_ports-1 generate
+  
+    FRAME_FIFO : generic_sync_fifo
+    generic map(
+      g_data_width  => 16,
+      g_size        => 1024,
+      g_with_empty  => true,
+      g_with_full   => true,
+      g_with_almost_empty  => false,
+      g_with_almost_full   => false,
+      g_with_count  => true)
+    port map(
+      rst_n_i => rst_n_i,
+      clk_i   => clk_sys_i,
+      d_i     => port_ffifo_in(i),
+      we_i    => port_ffifo_wr(i),
+      q_o     => port_ffifo_out(i),
+      rd_i    => port_ffifo_rd(i),
+      empty_o => open,
+      full_o  => port_ffifo_full(i));
+
+    SIZE_FIFO : generic_sync_fifo
+    generic map(
+      g_data_width  => 16,
+      g_size        => 8,
+      g_show_ahead  => true,
+      g_with_empty  => true,
+      g_with_full   => true,
+      g_with_almost_empty  => false,
+      g_with_almost_full   => false,
+      g_with_count  => true)
+    port map(
+      rst_n_i => rst_n_i,
+      clk_i   => clk_sys_i,
+      d_i     => port_sfifo_in(i),
+      we_i    => port_sfifo_wr(i),
+      q_o     => port_sfifo_out(i),
+      rd_i    => port_sfifo_rd(i),
+      empty_o => port_sfifo_empty(i),
+      full_o  => port_sfifo_full(i));
+
+  end generate gen_fifo;
+
+  -------------------------------------------
+  -- RX FSM
+  -------------------------------------------
+  gen_rxfsm : for i in 0 to g_num_ports-1 generate
+
+    port_fword_valid(i) <= '1' when(port_wrf_snk_i(i).cyc='1' and port_wrf_snk_i(i).stb='1' and port_wrf_snk_i(i).adr=c_WRF_DATA) else
+                           '0';
+
+    RX_FSM_P:process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if(rst_n_i = '0') then
+          port_fsize(i)    <= (others=>'0');
+          port_ffifo_wr(i) <= '0';
+          port_sfifo_wr(i) <= '0';
+          port_rxfsm(i)    <= IDLE;
+        else
+          port_ffifo_wr(i) <= '0';
+          port_sfifo_wr(i) <= '0';
+
+          if(port_fword_valid(i) = '1') then
+            port_wrf_snk_o(i).ack <= '1';
+          else
+            port_wrf_snk_o(i).ack <= '0';
+          end if;
+        
+          case port_rxfsm(i) is
+            when IDLE =>
+              if(port_wrf_snk_i(i).cyc='1' and port_ffifo_full(i)='0' and port_sfifo_full(i)='0') then
+                port_rxfsm(i) <= PAYLOAD;
+              elsif(port_wrf_snk_i(i).cyc='1') then
+                port_rxfsm(i) <= DROP;
+              end if;
+
+            when PAYLOAD =>
+              if port_fword_valid(i) = '1' then
+                if port_ffifo_full(i)='0' then
+                  port_ffifo_wr(i) <= '1';
+                  port_ffifo_in(i) <= port_wrf_snk_i(i).dat;
+                  if port_wrf_snk_i(i).sel = "11" then
+                    port_fsize(i) <= port_fsize(i) + 2;
+                  else
+                    port_fsize(i) <= port_fsize(i) + 1;    
+                  end if ;
+                else
+                  port_fsize(i) <= port_fsize(i)-2; --last write was already unsuccesfull
+                  port_rxfsm(i) <= DROP;  
+                end if ;
+              end if ;
+
+              if(port_wrf_snk_i(i).cyc='0') then
+                port_rxfsm(i) <= FEND;
+              end if;
+
+            when DROP =>
+              if(port_wrf_snk_i(i).cyc='0') then
+                port_rxfsm(i) <= FEND;
+              end if;
+
+            when FEND =>
+              if(port_fsize(i)>0) then
+                port_sfifo_wr(i) <= '1';
+                port_sfifo_in(i) <= std_logic_vector(port_fsize(i));
+                port_fsize(i) <= (others=>'0');
+              end if;
+              port_rxfsm(i) <= IDLE;
+          end case;
+        end if;
+      end if;
+    end process;
+
+    port_wrf_snk_o(i).stall <= '0';
+    port_wrf_snk_o(i).rty   <= '0';
+    port_wrf_snk_o(i).err   <= '0';
+
+  end generate gen_rxfsm;
+  -------------------------------------------
+  -- TX FSM
+  -------------------------------------------
+  gen_txfsm : for i in 0 to g_num_ports-1 generate
+    
+    WRF_SRC: ep_rx_wb_master
+      generic map(
+        g_ignore_ack => false,
+        g_cyc_on_stall => true)
+      port map(
+        clk_sys_i  => clk_sys_i,
+        rst_n_i    => rst_n_i,
+        snk_fab_i  => port_src_fab(i),
+        snk_dreq_o => port_src_dreq(i),
+        src_wb_i   => port_wrf_src_i(i),
+        src_wb_o   => port_wrf_src_o(i));
+
+    port_src_fab(i).has_rx_timestamp <= '0';
+    port_src_fab(i).rx_timestamp_valid <= '0';
+    port_src_fab(i).error <= '0';
+    port_src_fab(i).data <= port_ffifo_out(g_num_ports-1-i) when (port_txfsm(i)=PAYLOAD or port_txfsm(i)=EOF) else
+                          f_marshall_wrf_status(stored_status);
+    
+    TX_FSM_P:process(clk_sys_i)
+    begin
+      if rising_edge(clk_sys_i) then
+        if(rst_n_i='0') then
+          port_txfsm(i) <= IDLE;
+          port_txsize(i) <= (others=>'0');
+          port_ffifo_rd(g_num_ports-1-i) <= '0';
+          port_sfifo_rd(g_num_ports-1-i) <= '0';
+          port_src_fab(i).addr <= (others=>'0');
+          
+        else
+          port_sfifo_rd(g_num_ports-1-i) <= '0';
+          port_ffifo_rd(g_num_ports-1-i) <= '0';
+          port_src_fab(i).sof    <= '0';
+          port_src_fab(i).eof    <= '0';
+          port_src_fab(i).dvalid <= '0';
+
+          case port_txfsm(i) is
+            when IDLE =>
+              port_txsize(i)  <= (others=>'0');
+              port_src_fab(i).bytesel <= '0';
+              port_src_fab(i).addr    <= c_WRF_STATUS;
+
+              if(port_sfifo_empty(g_num_ports-1-i) = '0' and port_src_dreq(i)='1') then
+                port_sfifo_rd(g_num_ports-1-i) <= '1';
+                port_src_fab(i).sof <= '1';
+                port_txfsm(i)       <= GET_SIZE;
+              end if;
+
+            when GET_SIZE =>
+              port_txsize(i)    <= unsigned(port_sfifo_out(g_num_ports-1-i));
+              port_txfsm(i)     <= STATUS;
+              port_src_fab(i).dvalid <= '1';
+              port_ffifo_rd(g_num_ports-1-i) <= '1';
+            
+            when STATUS =>
+              if(port_src_dreq(i)='1') then
+                port_ffifo_rd(g_num_ports-1-i) <= '1';
+                port_src_fab(i).addr <= c_WRF_DATA;
+                port_txsize(i) <= port_txsize(i) - 2;
+                port_src_fab(i).dvalid <= '1';
+                port_txfsm(i) <= PAYLOAD;
+              end if;
+            
+            when PAYLOAD =>
+              if(port_src_dreq(i)='1' and port_txsize(i)>1) then
+                port_txsize(i) <= port_txsize(i) - 2;
+                port_src_fab(i).bytesel <= '0';
+              elsif(port_src_dreq(i)='1' and port_txsize(i)=1) then
+                port_txsize(i) <= port_txsize(i) - 1;
+                port_src_fab(i).bytesel <= '1';
+              end if;
+
+              if(port_src_dreq(i)='1' and port_txsize(i)>2) then
+                port_ffifo_rd(g_num_ports-1-i) <= '1';
+                port_src_fab(i).dvalid <= '1';
+              elsif( port_src_dreq(i)='1' and port_txsize(i)<=2) then
+                port_src_fab(i).dvalid <= '1';
+                port_txfsm(i)   <= EOF;
+              end if;
+
+            when EOF =>
+              if(port_src_dreq(i)='1') then
+                port_src_fab(i).eof <= '1';
+                port_txfsm(i) <= IDLE;
+              end if;
+
+            when others =>
+              port_txfsm(i) <= IDLE;
+          end case;
+        end if;
+      end if;
+    end process;
+
+  end generate gen_txfsm;
+
+end behav;
--- a/modules/wr_endpoint/endpoint_pkg.vhd
+++ b/modules/wr_endpoint/endpoint_pkg.vhd
@@ -432,7 +432,23 @@ package endpoint_pkg is
        version   => x"00000002",
        date      => x"20121116",
        name      => "WR-Endpoint        ")));
-
+  
+  constant c_dp_xwr_endpoint_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"650c2d4e",
+        version   => x"00000002",
+        date      => x"20121116",
+        name      => "WR-Endpoint-DP    ")));
+  
 end endpoint_pkg;

 package body endpoint_pkg is

--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -92,6 +92,7 @@ entity wr_core is
    g_softpll_enable_debugger   : boolean                        := false;
    g_vuart_fifo_size           : integer                        := 1024;
    g_pcs_16bit                 : boolean                        := false;
+    g_num_ports                 : integer                        := 1;
    g_records_for_phy           : boolean                        := false;
    g_diag_id                   : integer                        := 0;
    g_diag_ver                  : integer                        := 0;
@@ -303,6 +304,37 @@ entity wr_core is

    link_ok_o : out std_logic;

+    dp_phy8_o               : out t_phy_8bits_from_wrc;
+    dp_phy8_i               : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    dp_phy16_o              : out t_phy_16bits_from_wrc;
+    dp_phy16_i              : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+    dp_phy_ref_clk_i        : in  std_logic;
+    dp_phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_tx_disparity_i   : in  std_logic;
+    dp_phy_tx_enc_err_i     : in  std_logic;
+    dp_phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_rx_rbclk_i       : in  std_logic;
+    dp_phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_rx_enc_err_i     : in  std_logic;
+    dp_phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_rst_o            : out std_logic;
+    dp_phy_rdy_i            : in  std_logic := '1';
+    dp_phy_loopen_o         : out std_logic;
+    dp_phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    dp_phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    dp_phy_sfp_tx_fault_i   : in  std_logic := '0';
+    dp_phy_sfp_los_i        : in  std_logic := '0';
+    dp_phy_sfp_tx_disable_o : out std_logic;
+    dp_txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+    dp_txtsu_frame_id_o     : out std_logic_vector(15 downto 0);
+    dp_txtsu_ts_value_o     : out std_logic_vector(31 downto 0);
+    dp_txtsu_ts_incorrect_o : out std_logic;
+    dp_txtsu_stb_o          : out std_logic;
+    dp_txtsu_ack_i          : in  std_logic := '1';
+    dp_fc_tx_pause_req_i    : in  std_logic                     := '0';
+    dp_fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0) := x"0000";
+    dp_fc_tx_pause_ready_o  : out std_logic;
    -------------------------------------
    -- DIAG to/from external modules
    -------------------------------------
@@ -410,7 +442,8 @@ architecture struct of wr_core is
  -----------------------------------------------------------------------------
  --WB Secondary Crossbar
  -----------------------------------------------------------------------------
-  constant c_secbar_layout : t_sdb_record_array(8 downto 0) :=
+  constant c_nr_slaves_secbar : natural := 11;
+  constant c_secbar_layout : t_sdb_record_array(c_nr_slaves_secbar-1 downto 0) :=
    (0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
     1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
     2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
@@ -418,16 +451,18 @@ architecture struct of wr_core is
     4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"),  -- Syscon
     5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"),  -- UART
     6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"),  -- 1-Wire
-     7 => f_sdb_embed_device(g_aux_sdb,         x"00000700"),  -- aux WB bus
-     8 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000800")   -- WRPC diag registers
+     7 => f_sdb_embed_device(g_aux_sdb,        x"00000700"),   -- aux WB bus
+     8 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000800"),  -- WRPC diag registers     
+     9 => f_sdb_embed_device(c_dp_xwr_mini_nic_sdb, x"00000900"), -- dualport nic
+     10=> f_sdb_embed_device(c_dp_xwr_endpoint_sdb, x"00000A00")  -- dualport endpoint
     );

-  constant c_secbar_sdb_address : t_wishbone_address := x"00000C00";
+  constant c_secbar_sdb_address : t_wishbone_address := x"00001000";
  constant c_secbar_bridge_sdb  : t_sdb_bridge       :=
    f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);

-  signal secbar_master_i : t_wishbone_master_in_array(8 downto 0);
-  signal secbar_master_o : t_wishbone_master_out_array(8 downto 0);
+  signal secbar_master_i : t_wishbone_master_in_array(c_nr_slaves_secbar-1 downto 0);
+  signal secbar_master_o : t_wishbone_master_out_array(c_nr_slaves_secbar-1 downto 0);

  -----------------------------------------------------------------------------
  --WB intercon
@@ -480,12 +515,11 @@ architecture struct of wr_core is
  signal ep_snk_out : t_wrf_sink_out;
  signal ep_snk_in  : t_wrf_sink_in;

-
-  signal mux_src_out : t_wrf_source_out_array(1 downto 0);
-  signal mux_src_in  : t_wrf_source_in_array(1 downto 0);
-  signal mux_snk_out : t_wrf_sink_out_array(1 downto 0);
-  signal mux_snk_in  : t_wrf_sink_in_array(1 downto 0);
-  signal mux_class   : t_wrf_mux_class(1 downto 0);
+  signal mux_src_out : t_wrf_source_out_array(2 downto 0);
+  signal mux_src_in  : t_wrf_source_in_array(2 downto 0);
+  signal mux_snk_out : t_wrf_sink_out_array(2 downto 0);
+  signal mux_snk_in  : t_wrf_sink_in_array(2 downto 0);
+  signal mux_class   : t_wrf_mux_class(2 downto 0);

  signal spll_out_locked : std_logic_vector(g_aux_clks downto 0);

@@ -493,8 +527,40 @@ architecture struct of wr_core is
  signal dac_dpll_sel     : std_logic_vector(3 downto 0);
  signal dac_dpll_load_p1 : std_logic;

-  signal clk_fb     : std_logic_vector(g_aux_clks downto 0);
+  signal softpll_refclk : std_logic_vector(g_num_ports-1 downto 0);
+  signal softpll_clk_fb : std_logic_vector(g_aux_clks downto 0);
  signal out_enable : std_logic_vector(g_aux_clks downto 0);
+  
+  signal dp_phy_rst                : std_logic;
+  signal dp_phy_rx_clk             : std_logic;
+  signal dp_phy_tx_clk             : std_logic;
+  signal dp_ep_txtsu_port_id       : std_logic_vector(4 downto 0);
+  signal dp_ep_txtsu_frame_id      : std_logic_vector(15 downto 0);
+  signal dp_ep_txtsu_ts_value      : std_logic_vector(31 downto 0);
+  signal dp_ep_txtsu_ts_incorrect  : std_logic;
+  signal dp_ep_txtsu_stb           : std_logic;
+  signal dp_ep_txtsu_ack           : std_logic;
+  signal dp_ep_led_link            : std_logic;
+  signal dp_mnic_mem_data_o        : std_logic_vector(31 downto 0);
+  signal dp_mnic_mem_addr_o        : std_logic_vector(c_mnic_memsize_log2-1 downto 0);
+  signal dp_mnic_mem_wr_o          : std_logic;
+  signal dp_mnic_txtsu_ack         : std_logic;
+  signal dp_mnic_txtsu_stb         : std_logic;
+  signal dp_ep_wb_in               : t_wishbone_slave_in;
+  signal dp_ep_wb_out              : t_wishbone_slave_out;
+  signal dp_minic_wb_in            : t_wishbone_slave_in;
+  signal dp_minic_wb_out           : t_wishbone_slave_out;
+  signal dp_ep_src_out             : t_wrf_source_out;
+  signal dp_ep_src_in              : t_wrf_source_in;
+  signal dp_ep_snk_out             : t_wrf_sink_out;
+  signal dp_ep_snk_in              : t_wrf_sink_in;
+  signal dp_mux_src_out            : t_wrf_source_out_array(1 downto 0);
+  signal dp_mux_src_in             : t_wrf_source_in_array(1 downto 0);
+  signal dp_mux_snk_out            : t_wrf_sink_out_array(1 downto 0);
+  signal dp_mux_snk_in             : t_wrf_sink_in_array(1 downto 0);
+  signal dp_mux_class              : t_wrf_mux_class(1 downto 0);
+
+

  --component chipscope_ila
  --  port (
@@ -526,16 +592,28 @@ begin
  GEN_16BIT_PHY_IF: if g_pcs_16bit and g_records_for_phy generate
    phy_rx_clk <= phy16_i.rx_clk;
    phy_tx_clk <= phy16_i.ref_clk;
+
+    dp_phy_rx_clk <= dp_phy16_i.rx_clk;
+    dp_phy_tx_clk <= dp_phy16_i.ref_clk;
+
  end generate;

  GEN_8BIT_PHY_IF: if not g_pcs_16bit and g_records_for_phy generate
    phy_rx_clk <= phy8_i.rx_clk;
    phy_tx_clk <= phy8_i.ref_clk;
+
+    dp_phy_rx_clk <= dp_phy8_i.rx_clk;
+    dp_phy_tx_clk <= dp_phy8_i.ref_clk;
+
  end generate;

  GEN_STD_PHY_IF: if not g_records_for_phy generate
    phy_rx_clk <= phy_rx_rbclk_i;
    phy_tx_clk <= phy_ref_clk_i;
+
+    dp_phy_rx_clk <= phy_rx_rbclk_i;
+    dp_phy_tx_clk <= phy_ref_clk_i;
+
  end generate;

  -----------------------------------------------------------------------------
@@ -638,7 +716,7 @@ begin
      g_tag_bits             => 22,
      g_interface_mode       => PIPELINED,
      g_address_granularity  => BYTE,
-      g_num_ref_inputs       => 1,
+      g_num_ref_inputs       => g_num_ports,
      g_num_outputs          => 1 + g_aux_clks,
      g_ref_clock_rate       => f_refclk_rate(g_pcs_16bit),
      g_ext_clock_rate       => 10000000)
@@ -650,9 +728,9 @@ begin
      rst_dmtd_n_i => rst_net_resync_dmtd_n,

      -- Reference inputs (i.e. the RX clocks recovered by the PHYs)
-      clk_ref_i(0) => phy_rx_clk,
+      clk_ref_i    => softpll_refclk,
      -- Feedback clocks (i.e. the outputs of the main or aux oscillator)
-      clk_fb_i     => clk_fb,
+      clk_fb_i     => softpll_clk_fb,
      -- DMTD Offset clock
      clk_dmtd_i   => clk_dmtd_i,

@@ -686,8 +764,9 @@ begin

      debug_o => open);

-  clk_fb(0)                       <= clk_ref_i;
-  clk_fb(g_aux_clks downto 1)     <= clk_aux_i;
+  softpll_refclk(0)                       <= phy_rx_clk;
+  softpll_clk_fb(0)                       <= clk_ref_i;
+  softpll_clk_fb(g_aux_clks downto 1)     <= clk_aux_i;
  out_enable(0)                   <= '1';
  out_enable(g_aux_clks downto 1) <= tm_clk_aux_lock_en_i;

@@ -1035,7 +1114,7 @@ begin
  WB_SECONDARY_CON : xwb_sdb_crossbar
    generic map(
      g_num_masters => 1,
-      g_num_slaves  => 9,
+      g_num_slaves  => c_nr_slaves_secbar,
      g_registered  => true,
      g_wraparound  => true,
      g_layout      => c_secbar_layout,
@@ -1056,6 +1135,12 @@ begin
  minic_wb_in        <= secbar_master_o(0);
  secbar_master_i(1) <= ep_wb_out;
  ep_wb_in           <= secbar_master_o(1);
+
+  secbar_master_i(9) <= dp_minic_wb_out;
+  dp_minic_wb_in     <= secbar_master_o(9);
+  secbar_master_i(10) <= dp_ep_wb_out;
+  dp_ep_wb_in        <= secbar_master_o(10);
+
  secbar_master_i(2) <= spll_wb_out;
  spll_wb_in         <= secbar_master_o(2);
  secbar_master_i(3) <= ppsg_wb_out;
@@ -1107,7 +1192,7 @@ begin
  -----------------------------------------------------------------------------
  U_WBP_Mux : xwrf_mux
    generic map(
-      g_muxed_ports => 2)
+      g_muxed_ports => 3)
    port map (
      clk_sys_i   => clk_sys_i,
      rst_n_i     => rst_net_n,
@@ -1122,7 +1207,9 @@ begin
      mux_class_i => mux_class);

  mux_class(0)  <= x"0f";
-  mux_class(1)  <= x"f0";
+  mux_class(1)  <= x"30";
+  mux_class(2)  <= x"C0";
+
  ext_src_adr_o <= mux_src_out(1).adr;
  ext_src_dat_o <= mux_src_out(1).dat;
  ext_src_stb_o <= mux_src_out(1).stb;
@@ -1163,4 +1250,162 @@ begin

  ep_txtsu_ack <= txtsu_ack_i or mnic_txtsu_ack;

+  --------------------------------------------------------------------
+  ------------------  Dual Port Part ---------------------------------
+  --------------------------------------------------------------------
+
+  GEN_DUALPORT : if (g_num_ports = 2) generate
+    
+    softpll_refclk(1)  <= dp_phy_rx_clk;
+
+    dp_phy_rst_o <= dp_phy_rst;
+
+    DP_U_Endpoint : xwr_endpoint
+      generic map (
+        g_interface_mode      => PIPELINED,
+        g_address_granularity => BYTE,
+        g_simulation          => f_int2bool(g_simulation),
+        g_tx_runt_padding     => g_tx_runt_padding,
+        g_pcs_16bit           => g_pcs_16bit,
+        g_records_for_phy     => g_records_for_phy,
+        g_rx_buffer_size      => g_rx_buffer_size,
+        g_with_rx_buffer      => true,
+        g_with_flow_control   => false,
+        g_with_timestamper    => true,
+        g_with_dpi_classifier => true,
+        g_with_vlans          => false,
+        g_with_rtu            => false,
+        g_with_leds           => true,
+        g_with_packet_injection => false,
+        g_use_new_rxcrc       => true,
+        g_use_new_txcrc       => false)
+      port map (
+        clk_ref_i            => clk_ref_i,
+        clk_sys_i            => clk_sys_i,
+        clk_dmtd_i           => clk_dmtd_i,
+        rst_sys_n_i          => rst_net_n,
+        rst_ref_n_i          => rst_net_resync_ref_n,
+        rst_dmtd_n_i         => rst_net_resync_dmtd_n,
+        rst_txclk_n_i        => rst_net_resync_txclk_n,
+        rst_rxclk_n_i        => rst_net_resync_rxclk_n,
+        pps_csync_p1_i       => s_pps_csync,
+        pps_valid_i          => pps_valid,
+        phy_rst_o            => dp_phy_rst,
+        phy_rdy_i            => dp_phy_rdy_i,
+        phy_loopen_o         => dp_phy_loopen_o,
+        phy_loopen_vec_o     => dp_phy_loopen_vec_o,
+        phy_tx_prbs_sel_o    => dp_phy_tx_prbs_sel_o,
+        phy_sfp_tx_fault_i   => dp_phy_sfp_tx_fault_i,
+        phy_sfp_los_i        => dp_phy_sfp_los_i,
+        phy_sfp_tx_disable_o => dp_phy_sfp_tx_disable_o,
+        phy_ref_clk_i        => dp_phy_ref_clk_i,
+        phy_tx_data_o        => dp_phy_tx_data_o,
+        phy_tx_k_o           => dp_phy_tx_k_o,
+        phy_tx_disparity_i   => dp_phy_tx_disparity_i,
+        phy_tx_enc_err_i     => dp_phy_tx_enc_err_i,
+        phy_rx_data_i        => dp_phy_rx_data_i,
+        phy_rx_clk_i         => dp_phy_rx_rbclk_i,
+        phy_rx_k_i           => dp_phy_rx_k_i,
+        phy_rx_enc_err_i     => dp_phy_rx_enc_err_i,
+        phy_rx_bitslide_i    => dp_phy_rx_bitslide_i,
+        phy8_o               => dp_phy8_o,
+        phy8_i               => dp_phy8_i,
+        phy16_o              => dp_phy16_o,
+        phy16_i              => dp_phy16_i,
+        src_o                => dp_ep_src_out,
+        src_i                => dp_ep_src_in,
+        snk_o                => dp_ep_snk_out,
+        snk_i                => dp_ep_snk_in,
+        txtsu_port_id_o      => dp_ep_txtsu_port_id,
+        txtsu_frame_id_o     => dp_ep_txtsu_frame_id,
+        txtsu_ts_value_o     => dp_ep_txtsu_ts_value,
+        txtsu_ts_incorrect_o => dp_ep_txtsu_ts_incorrect,
+        txtsu_stb_o          => dp_ep_txtsu_stb,
+        txtsu_ack_i          => dp_ep_txtsu_ack,
+        wb_i                 => dp_ep_wb_in,
+        wb_o                 => dp_ep_wb_out,
+        -- rmon_events_o        => open,
+        -- txts_o               => abscal_txts_o,
+        -- rxts_o               => abscal_rxts_o,
+        fc_tx_pause_req_i    => dp_fc_tx_pause_req_i,
+        fc_tx_pause_delay_i  => dp_fc_tx_pause_delay_i,
+        fc_tx_pause_ready_o  => dp_fc_tx_pause_ready_o,
+        led_link_o           => dp_ep_led_link,
+        led_act_o            => open
+        );
+
+    dp_mini_nic : xwr_mini_nic
+      generic map (
+        g_interface_mode       => pipelined,
+        g_address_granularity  => byte,
+        g_tx_fifo_size         => 1024,
+        g_rx_fifo_size         => 2048,
+        g_buffer_little_endian => false)
+      port map (
+        clk_sys_i              => clk_sys_i,
+        rst_n_i                => rst_net_n,
+        src_o                  => dp_mux_snk_in(0),
+        src_i                  => dp_mux_snk_out(0),
+        snk_o                  => dp_mux_src_in(0),
+        snk_i                  => dp_mux_src_out(0),
+        txtsu_port_id_i        => dp_ep_txtsu_port_id,
+        txtsu_frame_id_i       => dp_ep_txtsu_frame_id,
+        txtsu_tsval_i          => dp_ep_txtsu_ts_value,
+        txtsu_tsincorrect_i    => dp_ep_txtsu_ts_incorrect,
+        txtsu_stb_i            => dp_mnic_txtsu_stb,
+        txtsu_ack_o            => dp_mnic_txtsu_ack,
+        wb_i                   => dp_minic_wb_in,
+        wb_o                   => dp_minic_wb_out
+        );
+    
+    DP_U_WBP_Mux : xwrf_mux
+      generic map(
+        g_muxed_ports => 2)
+      port map (
+        clk_sys_i   => clk_sys_i,
+        rst_n_i     => rst_net_n,
+        ep_src_o    => dp_ep_snk_in,
+        ep_src_i    => dp_ep_snk_out,
+        ep_snk_o    => dp_ep_src_in,
+        ep_snk_i    => dp_ep_src_out,
+        mux_src_o   => dp_mux_src_out,
+        mux_src_i   => dp_mux_src_in,
+        mux_snk_o   => dp_mux_snk_out,
+        mux_snk_i   => dp_mux_snk_in,
+        mux_class_i => dp_mux_class);
+
+    dp_mux_class(0)  <= x"0f";
+    dp_mux_class(1)  <= x"f0";
+    
+    dp_txtsu_port_id_o      <= dp_ep_txtsu_port_id;
+    dp_txtsu_frame_id_o     <= dp_ep_txtsu_frame_id;
+    dp_txtsu_ts_value_o     <= dp_ep_txtsu_ts_value;
+    dp_txtsu_ts_incorrect_o <= dp_ep_txtsu_ts_incorrect;
+
+    -- ts goes to external I/F
+    dp_txtsu_stb_o          <= '1' when (dp_ep_txtsu_stb = '1' and (dp_ep_txtsu_frame_id /= x"0000")) else
+                            '0';
+    -- ts goes to minic
+    dp_mnic_txtsu_stb      <=  '1' when (dp_ep_txtsu_stb = '1' and (dp_ep_txtsu_frame_id  = x"0000")) else
+                            '0';
+
+    dp_ep_txtsu_ack <= dp_txtsu_ack_i or dp_mnic_txtsu_ack;    
+
+    U_DP_SWITCH : xwrf_dp_switch
+      generic map (
+        g_num_ports     => g_num_ports)
+      port map (
+        clk_sys_i       => clk_sys_i,
+        rst_n_i         => rst_net_n,
+        port_wrf_snk_i(0)  => mux_src_out(2),
+        port_wrf_snk_i(1)  => dp_mux_src_out(1),
+        port_wrf_snk_o(0)  => mux_src_in(2),
+        port_wrf_snk_o(1)  => dp_mux_src_in(1),
+        port_wrf_src_o(0)  => mux_snk_in(2),
+        port_wrf_src_o(1)  => dp_mux_snk_in(1),
+        port_wrf_src_i(0)  => mux_snk_out(2),
+        port_wrf_src_i(1)  => dp_mux_snk_out(1));
+
+  end generate;
+
 end struct;
--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
@@ -113,6 +113,22 @@ package wrcore_pkg is
        version   => x"00000001",
        date      => x"20120305",
        name      => "WR-Mini-NIC        ")));
+  
+  constant c_dp_xwr_mini_nic_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"a224633b",
+        version   => x"00000001",
+        date      => x"20120305",
+        name      => "WR-Mini-NIC-DP     ")));

  component xwr_mini_nic
    generic (
@@ -383,6 +399,7 @@ package wrcore_pkg is
      g_softpll_enable_debugger   : boolean                        := false;
      g_vuart_fifo_size           : integer                        := 1024;
      g_pcs_16bit                 : boolean                        := false;
+      g_num_ports                 : integer                        := 1;
      g_records_for_phy           : boolean                        := false;
      g_diag_id                   : integer                        := 0;
      g_diag_ver                  : integer                        := 0;
@@ -502,6 +519,33 @@ package wrcore_pkg is

      link_ok_o : out std_logic;

+      dp_phy8_o               : out t_phy_8bits_from_wrc;
+      dp_phy8_i               : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+      dp_phy16_o              : out t_phy_16bits_from_wrc;
+      dp_phy16_i              : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+      dp_phy_ref_clk_i        : in  std_logic;
+      dp_phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_tx_disparity_i   : in  std_logic;
+      dp_phy_tx_enc_err_i     : in  std_logic;
+      dp_phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_rx_rbclk_i       : in  std_logic;
+      dp_phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_rx_enc_err_i     : in  std_logic;
+      dp_phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_rst_o            : out std_logic;
+      dp_phy_rdy_i            : in  std_logic := '1';
+      dp_phy_loopen_o         : out std_logic;
+      dp_phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      dp_phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      dp_phy_sfp_tx_fault_i   : in  std_logic := '0';
+      dp_phy_sfp_los_i        : in  std_logic := '0';
+      dp_phy_sfp_tx_disable_o : out std_logic;
+      dp_timestamps_o         : out t_txtsu_timestamp;
+      dp_timestamps_ack_i     : in  std_logic := '1';
+      dp_fc_tx_pause_req_i    : in  std_logic                     := '0';
+      dp_fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0) := x"0000";
+      dp_fc_tx_pause_ready_o  : out std_logic;
      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
      );
@@ -530,6 +574,7 @@ package wrcore_pkg is
      g_softpll_enable_debugger   : boolean                        := false;
      g_vuart_fifo_size           : integer                        := 1024;
      g_pcs_16bit                 : boolean                        := false;
+      g_num_ports                 : integer                        := 1;
      g_records_for_phy           : boolean                        := false;
      g_diag_id                   : integer                        := 0;
      g_diag_ver                  : integer                        := 0;
@@ -744,6 +789,37 @@ package wrcore_pkg is

      link_ok_o : out std_logic;

+      dp_phy8_o               : out t_phy_8bits_from_wrc;
+      dp_phy8_i               : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+      dp_phy16_o              : out t_phy_16bits_from_wrc;
+      dp_phy16_i              : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+      dp_phy_ref_clk_i        : in  std_logic;
+      dp_phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_tx_disparity_i   : in  std_logic;
+      dp_phy_tx_enc_err_i     : in  std_logic;
+      dp_phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_rx_rbclk_i       : in  std_logic;
+      dp_phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_rx_enc_err_i     : in  std_logic;
+      dp_phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+      dp_phy_rst_o            : out std_logic;
+      dp_phy_rdy_i            : in  std_logic := '1';
+      dp_phy_loopen_o         : out std_logic;
+      dp_phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+      dp_phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      dp_phy_sfp_tx_fault_i   : in  std_logic := '0';
+      dp_phy_sfp_los_i        : in  std_logic := '0';
+      dp_phy_sfp_tx_disable_o : out std_logic;
+      dp_txtsu_port_id_o      : out std_logic_vector(4 downto 0);
+      dp_txtsu_frame_id_o     : out std_logic_vector(15 downto 0);
+      dp_txtsu_ts_value_o     : out std_logic_vector(31 downto 0);
+      dp_txtsu_ts_incorrect_o : out std_logic;
+      dp_txtsu_stb_o          : out std_logic;
+      dp_txtsu_ack_i          : in  std_logic := '1';
+      dp_fc_tx_pause_req_i    : in  std_logic                     := '0';
+      dp_fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0) := x"0000";
+      dp_fc_tx_pause_ready_o  : out std_logic;
      -------------------------------------
      -- DIAG to/from external modules
      -------------------------------------

--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
@@ -91,6 +91,7 @@ entity xwr_core is
    g_softpll_enable_debugger   : boolean                        := false;
    g_vuart_fifo_size           : integer                        := 1024;
    g_pcs_16bit                 : boolean                        := false;
+    g_num_ports                 : integer                        := 1;
    g_records_for_phy           : boolean                        := false;
    g_diag_id                   : integer                        := 0;
    g_diag_ver                  : integer                        := 0;
@@ -269,7 +270,35 @@ entity xwr_core is
    aux_diag_i    : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
    aux_diag_o    : out t_generic_word_array(g_diag_rw_size-1 downto 0);

-    link_ok_o : out std_logic
+    link_ok_o : out std_logic;
+
+    dp_phy8_o               : out t_phy_8bits_from_wrc;
+    dp_phy8_i               : in  t_phy_8bits_to_wrc  := c_dummy_phy8_to_wrc;
+    dp_phy16_o              : out t_phy_16bits_from_wrc;
+    dp_phy16_i              : in  t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
+    dp_phy_ref_clk_i        : in  std_logic;
+    dp_phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_tx_k_o           : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_tx_disparity_i   : in  std_logic;
+    dp_phy_tx_enc_err_i     : in  std_logic;
+    dp_phy_rx_data_i        : in  std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_rx_rbclk_i       : in  std_logic;
+    dp_phy_rx_k_i           : in  std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_rx_enc_err_i     : in  std_logic;
+    dp_phy_rx_bitslide_i    : in  std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+    dp_phy_rst_o            : out std_logic;
+    dp_phy_rdy_i            : in  std_logic := '1';
+    dp_phy_loopen_o         : out std_logic;
+    dp_phy_loopen_vec_o     : out std_logic_vector(2 downto 0);
+    dp_phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    dp_phy_sfp_tx_fault_i   : in  std_logic := '0';
+    dp_phy_sfp_los_i        : in  std_logic := '0';
+    dp_phy_sfp_tx_disable_o : out std_logic;
+    dp_timestamps_o         : out t_txtsu_timestamp;
+    dp_timestamps_ack_i     : in  std_logic := '1';
+    dp_fc_tx_pause_req_i    : in  std_logic                     := '0';
+    dp_fc_tx_pause_delay_i  : in  std_logic_vector(15 downto 0) := x"0000";
+    dp_fc_tx_pause_ready_o  : out std_logic
    );
 end xwr_core;

@@ -296,6 +325,7 @@ begin
      g_softpll_enable_debugger   => g_softpll_enable_debugger,
      g_vuart_fifo_size           => g_vuart_fifo_size,
      g_pcs_16bit                 => g_pcs_16bit,
+      g_num_ports                 => g_num_ports,
      g_records_for_phy           => g_records_for_phy,
      g_diag_id                   => g_diag_id,
      g_diag_ver                  => g_diag_ver,
@@ -446,10 +476,43 @@ begin
      link_ok_o => link_ok_o,

      aux_diag_i => aux_diag_i,
-      aux_diag_o => aux_diag_o
+      aux_diag_o => aux_diag_o,
+
+      dp_phy8_o                => dp_phy8_o,
+      dp_phy8_i                => dp_phy8_i,
+      dp_phy16_o               => dp_phy16_o,
+      dp_phy16_i               => dp_phy16_i,
+      dp_phy_ref_clk_i         => dp_phy_ref_clk_i,
+      dp_phy_tx_data_o         => dp_phy_tx_data_o,
+      dp_phy_tx_k_o            => dp_phy_tx_k_o,
+      dp_phy_tx_disparity_i    => dp_phy_tx_disparity_i,
+      dp_phy_tx_enc_err_i      => dp_phy_tx_enc_err_i,
+      dp_phy_rx_data_i         => dp_phy_rx_data_i,
+      dp_phy_rx_rbclk_i        => dp_phy_rx_rbclk_i,
+      dp_phy_rx_k_i            => dp_phy_rx_k_i,
+      dp_phy_rx_enc_err_i      => dp_phy_rx_enc_err_i,
+      dp_phy_rx_bitslide_i     => dp_phy_rx_bitslide_i,
+      dp_phy_rst_o             => dp_phy_rst_o,
+      dp_phy_rdy_i             => dp_phy_rdy_i,
+      dp_phy_loopen_o          => dp_phy_loopen_o,
+      dp_phy_loopen_vec_o      => dp_phy_loopen_vec_o,
+      dp_phy_tx_prbs_sel_o     => dp_phy_tx_prbs_sel_o,
+      dp_phy_sfp_tx_fault_i    => dp_phy_sfp_tx_fault_i,
+      dp_phy_sfp_los_i         => dp_phy_sfp_los_i,
+      dp_phy_sfp_tx_disable_o  => dp_phy_sfp_tx_disable_o,
+      dp_txtsu_port_id_o       => dp_timestamps_o.port_id(4 downto 0),
+      dp_txtsu_frame_id_o      => dp_timestamps_o.frame_id,
+      dp_txtsu_ts_value_o      => dp_timestamps_o.tsval,
+      dp_txtsu_ts_incorrect_o  => dp_timestamps_o.incorrect,
+      dp_txtsu_stb_o           => dp_timestamps_o.stb,
+      dp_txtsu_ack_i           => dp_timestamps_ack_i,
+      dp_fc_tx_pause_req_i     => dp_fc_tx_pause_req_i,
+      dp_fc_tx_pause_delay_i   => dp_fc_tx_pause_delay_i,
+      dp_fc_tx_pause_ready_o   => dp_fc_tx_pause_ready_o
      );

  timestamps_o.port_id(5) <= '0';
+  dp_timestamps_o.port_id(5) <= '0';

  wrf_snk_o.rty <= '0';