Skip to content

W
White Rabbit core collection
Commit 3654cd97 authored by li hongming's avatar li hongming
Browse files
Options

Add generic parameter g_num_ports for WRPC. 

    Add extra MINIC/Endpoint in WRPC.
    Add a simple dualport switch module.
parent 9a125269
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 926 additions and 32 deletions
board/common/wr_board_pkg.vhd
View file @ 3654cd97
......@@ -111,6 +111,7 @@ package wr_board_pkg is
g_softpll_enable_debugger : boolean := FALSE;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := FALSE;
g_num_ports : integer := 1;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -210,7 +211,17 @@ package wr_board_pkg is
pps_csync_o : out std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
link_ok_o : out std_logic;
dp_phy8_o : out t_phy_8bits_from_wrc;
dp_phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
dp_phy16_o : out t_phy_16bits_from_wrc;
dp_phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
dp_timestamps_o : out t_txtsu_timestamp;
dp_timestamps_ack_i : in std_logic := '1';
dp_fc_tx_pause_req_i : in std_logic := '0';
dp_fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
dp_fc_tx_pause_ready_o : out std_logic
);
end component xwrc_board_common;
end wr_board_pkg;
......
board/common/xwrc_board_common.vhd
View file @ 3654cd97
......@@ -66,6 +66,7 @@ entity xwrc_board_common is
g_softpll_enable_debugger : boolean := FALSE;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := FALSE;
g_num_ports : integer := 1;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -261,7 +262,21 @@ entity xwrc_board_common is
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
link_ok_o : out std_logic;
---------------------------------------------------------------------------
-- Another PHY I/f for dualport
---------------------------------------------------------------------------
dp_phy8_o : out t_phy_8bits_from_wrc;
dp_phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
dp_phy16_o : out t_phy_16bits_from_wrc;
dp_phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
dp_timestamps_o : out t_txtsu_timestamp;
dp_timestamps_ack_i : in std_logic := '1';
dp_fc_tx_pause_req_i : in std_logic := '0';
dp_fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
dp_fc_tx_pause_ready_o : out std_logic
);
end entity xwrc_board_common;
......@@ -381,6 +396,7 @@ begin -- architecture struct
g_softpll_enable_debugger => g_softpll_enable_debugger,
g_vuart_fifo_size => g_vuart_fifo_size,
g_pcs_16bit => g_pcs_16bit,
g_num_ports => g_num_ports,
g_records_for_phy => TRUE,
g_diag_id => c_diag_id,
g_diag_ver => c_diag_ver,
......@@ -480,7 +496,35 @@ begin -- architecture struct
rst_aux_n_o => aux_rst_n,
aux_diag_i => aux_diag_in,
aux_diag_o => aux_diag_out,
link_ok_o => link_ok);
link_ok_o => link_ok,
dp_phy8_o => dp_phy8_o,
dp_phy8_i => dp_phy8_i,
dp_phy16_o => dp_phy16_o,
dp_phy16_i => dp_phy16_i,
dp_phy_ref_clk_i => '0',
dp_phy_tx_data_o => open,
dp_phy_tx_k_o => open,
dp_phy_tx_disparity_i=> '0',
dp_phy_tx_enc_err_i => '0',
dp_phy_rx_data_i => (others => '0'),
dp_phy_rx_rbclk_i => '0',
dp_phy_rx_k_i => (others => '0'),
dp_phy_rx_enc_err_i => '0',
dp_phy_rx_bitslide_i => (others => '0'),
dp_phy_rst_o => open,
dp_phy_rdy_i => '1',
dp_phy_loopen_o => open,
dp_phy_loopen_vec_o => open,
dp_phy_tx_prbs_sel_o => open,
dp_phy_sfp_tx_fault_i=> '0',
dp_phy_sfp_los_i => '0',
dp_phy_sfp_tx_disable_o => open,
dp_timestamps_o => dp_timestamps_o,
dp_timestamps_ack_i => dp_timestamps_ack_i,
dp_fc_tx_pause_req_i => dp_fc_tx_pause_req_i,
dp_fc_tx_pause_delay_i => dp_fc_tx_pause_delay_i,
dp_fc_tx_pause_ready_o => dp_fc_tx_pause_ready_o
);
link_ok_o <= link_ok;
tm_time_valid_o <= tm_time_valid;
......
board/cute/wr_cute_pkg.vhd
View file @ 3654cd97
......@@ -65,7 +65,9 @@ package wr_cute_pkg is
g_sfp0_enable : integer := 1;
g_sfp1_enable : integer := 0;
g_phy_refclk_sel : integer := 0;
g_multiboot_enable : boolean := false);
g_multiboot_enable : boolean := false;
g_num_ports : integer := 1
);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
......
board/cute/xwrc_board_cute.vhd
View file @ 3654cd97
......@@ -83,7 +83,8 @@ entity xwrc_board_cute is
g_sfp0_enable : integer := 1;
g_sfp1_enable : integer := 0;
g_phy_refclk_sel : integer := 0;
g_multiboot_enable : boolean := false
g_multiboot_enable : boolean := false;
g_num_ports : integer := 1
);
port (
---------------------------------------------------------------------------
......@@ -277,7 +278,13 @@ entity xwrc_board_cute is
pps_led_o : out std_logic;
pps_csync_o: out std_logic;
-- Link ok indication
link_ok_o : out std_logic
link_ok_o : out std_logic;
dp_timestamps_o : out t_txtsu_timestamp;
dp_timestamps_ack_i : in std_logic := '1';
dp_fc_tx_pause_req_i : in std_logic := '0';
dp_fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
dp_fc_tx_pause_ready_o : out std_logic
);
end entity xwrc_board_cute;
......@@ -402,6 +409,9 @@ architecture struct of xwrc_board_cute is
signal sfp1_tx_disable_out : std_logic;
signal sfp1_los_in : std_logic;
signal dp_phy8_to_wrc : t_phy_8bits_to_wrc;
signal dp_phy8_from_wrc : t_phy_8bits_from_wrc;
signal tm_time_valid : std_logic;
-- ext 10M clock output
......@@ -557,6 +567,30 @@ begin -- architecture struct
sfp1_tx_fault_in <= sfp1_tx_fault_i;
sfp1_los_in <= sfp1_los_i;
dp_cmp_xwrc_platform : xwrc_platform_xilinx
generic map (
g_fpga_family => "spartan6",
g_with_external_clock_input => false,
g_use_default_plls => false,
g_gtp_enable_ch0 => 0,
g_gtp_enable_ch1 => 1,
g_phy_refclk_sel => g_phy_refclk_sel,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
clk_125m_gtp_p_i => clk_125m_gtp1_p_i,
clk_125m_gtp_n_i => clk_125m_gtp1_n_i,
clk_125m_ref_i => clk_pll_125m,
sfp_txn_o => sfp1_txn_out,
sfp_txp_o => sfp1_txp_out,
sfp_rxn_i => sfp1_rxn_in,
sfp_rxp_i => sfp1_rxp_in,
sfp_tx_fault_i => sfp1_tx_fault_in,
sfp_los_i => sfp1_los_in,
sfp_tx_disable_o => sfp1_tx_disable_out,
phy8_o => dp_phy8_to_wrc,
phy8_i => dp_phy8_from_wrc);
end generate;
sfp0_rate_select_o <= '1';
......@@ -668,7 +702,8 @@ begin -- architecture struct
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_fabric_iface => g_fabric_iface
g_fabric_iface => g_fabric_iface,
g_num_ports => g_num_ports
)
port map (
clk_sys_i => clk_pll_62m5,
......@@ -757,7 +792,15 @@ begin -- architecture struct
pps_p_o => pps_p_o,
pps_csync_o => pps_csync,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o);
link_ok_o => link_ok_o,
dp_phy8_o => dp_phy8_from_wrc,
dp_phy8_i => dp_phy8_to_wrc,
dp_timestamps_o => dp_timestamps_o,
dp_timestamps_ack_i => dp_timestamps_ack_i,
dp_fc_tx_pause_req_i => dp_fc_tx_pause_req_i,
dp_fc_tx_pause_delay_i => dp_fc_tx_pause_delay_i,
dp_fc_tx_pause_ready_o => dp_fc_tx_pause_ready_o
);
tm_time_valid_o <= tm_time_valid;
pps_csync_o <= pps_csync;
......
modules/fabric/wr_fabric_pkg.vhd
View file @ 3654cd97
......@@ -187,7 +187,26 @@ package wr_fabric_pkg is
bytesel_i : in std_logic;
dreq_o : out std_logic);
end component;
component xwrf_dp_switch is
generic(
-- g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer := 2 );
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- wb_i : in t_wishbone_slave_in;
-- wb_o : out t_wishbone_slave_out;
port_wrf_snk_i : in t_wrf_sink_in_array(g_num_ports-1 downto 0);
port_wrf_snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
port_wrf_src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
port_wrf_src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0)
);
end component;
end wr_fabric_pkg;
package body wr_fabric_pkg is
......
modules/fabric/xwrf_dp_switch/xwrf_dp_switch.vhd 0 → 100644
View file @ 3654cd97
This diff is collapsed.
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 3654cd97
......@@ -432,7 +432,23 @@ package endpoint_pkg is
version => x"00000002",
date => x"20121116",
name => "WR-Endpoint ")));
constant c_dp_xwr_endpoint_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"650c2d4e",
version => x"00000002",
date => x"20121116",
name => "WR-Endpoint-DP ")));
end endpoint_pkg;
package body endpoint_pkg is
......
modules/wrc_core/wr_core.vhd
View file @ 3654cd97
This diff is collapsed.
modules/wrc_core/wrcore_pkg.vhd
View file @ 3654cd97
......@@ -113,6 +113,22 @@ package wrcore_pkg is
version => x"00000001",
date => x"20120305",
name => "WR-Mini-NIC ")));
constant c_dp_xwr_mini_nic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"a224633b",
version => x"00000001",
date => x"20120305",
name => "WR-Mini-NIC-DP ")));
component xwr_mini_nic
generic (
......@@ -383,6 +399,7 @@ package wrcore_pkg is
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_num_ports : integer := 1;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -502,6 +519,33 @@ package wrcore_pkg is
link_ok_o : out std_logic;
dp_phy8_o : out t_phy_8bits_from_wrc;
dp_phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
dp_phy16_o : out t_phy_16bits_from_wrc;
dp_phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
dp_phy_ref_clk_i : in std_logic;
dp_phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
dp_phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
dp_phy_tx_disparity_i : in std_logic;
dp_phy_tx_enc_err_i : in std_logic;
dp_phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
dp_phy_rx_rbclk_i : in std_logic;
dp_phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
dp_phy_rx_enc_err_i : in std_logic;
dp_phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
dp_phy_rst_o : out std_logic;
dp_phy_rdy_i : in std_logic := '1';
dp_phy_loopen_o : out std_logic;
dp_phy_loopen_vec_o : out std_logic_vector(2 downto 0);
dp_phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
dp_phy_sfp_tx_fault_i : in std_logic := '0';
dp_phy_sfp_los_i : in std_logic := '0';
dp_phy_sfp_tx_disable_o : out std_logic;
dp_timestamps_o : out t_txtsu_timestamp;
dp_timestamps_ack_i : in std_logic := '1';
dp_fc_tx_pause_req_i : in std_logic := '0';
dp_fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
dp_fc_tx_pause_ready_o : out std_logic;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0)
);
......@@ -530,6 +574,7 @@ package wrcore_pkg is
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_num_ports : integer := 1;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -744,6 +789,37 @@ package wrcore_pkg is
link_ok_o : out std_logic;
dp_phy8_o : out t_phy_8bits_from_wrc;
dp_phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
dp_phy16_o : out t_phy_16bits_from_wrc;
dp_phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
dp_phy_ref_clk_i : in std_logic;
dp_phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
dp_phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
dp_phy_tx_disparity_i : in std_logic;
dp_phy_tx_enc_err_i : in std_logic;
dp_phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
dp_phy_rx_rbclk_i : in std_logic;
dp_phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
dp_phy_rx_enc_err_i : in std_logic;
dp_phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
dp_phy_rst_o : out std_logic;
dp_phy_rdy_i : in std_logic := '1';
dp_phy_loopen_o : out std_logic;
dp_phy_loopen_vec_o : out std_logic_vector(2 downto 0);
dp_phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
dp_phy_sfp_tx_fault_i : in std_logic := '0';
dp_phy_sfp_los_i : in std_logic := '0';
dp_phy_sfp_tx_disable_o : out std_logic;
dp_txtsu_port_id_o : out std_logic_vector(4 downto 0);
dp_txtsu_frame_id_o : out std_logic_vector(15 downto 0);
dp_txtsu_ts_value_o : out std_logic_vector(31 downto 0);
dp_txtsu_ts_incorrect_o : out std_logic;
dp_txtsu_stb_o : out std_logic;
dp_txtsu_ack_i : in std_logic := '1';
dp_fc_tx_pause_req_i : in std_logic := '0';
dp_fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
dp_fc_tx_pause_ready_o : out std_logic;
-------------------------------------
-- DIAG to/from external modules
-------------------------------------
......
modules/wrc_core/xwr_core.vhd
View file @ 3654cd97
......@@ -91,6 +91,7 @@ entity xwr_core is
g_softpll_enable_debugger : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_num_ports : integer := 1;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -269,7 +270,35 @@ entity xwr_core is
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others =>(others=>'0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
link_ok_o : out std_logic
link_ok_o : out std_logic;
dp_phy8_o : out t_phy_8bits_from_wrc;
dp_phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
dp_phy16_o : out t_phy_16bits_from_wrc;
dp_phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
dp_phy_ref_clk_i : in std_logic;
dp_phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
dp_phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
dp_phy_tx_disparity_i : in std_logic;
dp_phy_tx_enc_err_i : in std_logic;
dp_phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
dp_phy_rx_rbclk_i : in std_logic;
dp_phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
dp_phy_rx_enc_err_i : in std_logic;
dp_phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
dp_phy_rst_o : out std_logic;
dp_phy_rdy_i : in std_logic := '1';
dp_phy_loopen_o : out std_logic;
dp_phy_loopen_vec_o : out std_logic_vector(2 downto 0);
dp_phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
dp_phy_sfp_tx_fault_i : in std_logic := '0';
dp_phy_sfp_los_i : in std_logic := '0';
dp_phy_sfp_tx_disable_o : out std_logic;
dp_timestamps_o : out t_txtsu_timestamp;
dp_timestamps_ack_i : in std_logic := '1';
dp_fc_tx_pause_req_i : in std_logic := '0';
dp_fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
dp_fc_tx_pause_ready_o : out std_logic
);
end xwr_core;
......@@ -296,6 +325,7 @@ begin
g_softpll_enable_debugger => g_softpll_enable_debugger,
g_vuart_fifo_size => g_vuart_fifo_size,
g_pcs_16bit => g_pcs_16bit,
g_num_ports => g_num_ports,
g_records_for_phy => g_records_for_phy,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
......@@ -446,10 +476,43 @@ begin
link_ok_o => link_ok_o,
aux_diag_i => aux_diag_i,
aux_diag_o => aux_diag_o
aux_diag_o => aux_diag_o,
dp_phy8_o => dp_phy8_o,
dp_phy8_i => dp_phy8_i,
dp_phy16_o => dp_phy16_o,
dp_phy16_i => dp_phy16_i,
dp_phy_ref_clk_i => dp_phy_ref_clk_i,
dp_phy_tx_data_o => dp_phy_tx_data_o,
dp_phy_tx_k_o => dp_phy_tx_k_o,
dp_phy_tx_disparity_i => dp_phy_tx_disparity_i,
dp_phy_tx_enc_err_i => dp_phy_tx_enc_err_i,
dp_phy_rx_data_i => dp_phy_rx_data_i,
dp_phy_rx_rbclk_i => dp_phy_rx_rbclk_i,
dp_phy_rx_k_i => dp_phy_rx_k_i,
dp_phy_rx_enc_err_i => dp_phy_rx_enc_err_i,
dp_phy_rx_bitslide_i => dp_phy_rx_bitslide_i,
dp_phy_rst_o => dp_phy_rst_o,
dp_phy_rdy_i => dp_phy_rdy_i,
dp_phy_loopen_o => dp_phy_loopen_o,
dp_phy_loopen_vec_o => dp_phy_loopen_vec_o,
dp_phy_tx_prbs_sel_o => dp_phy_tx_prbs_sel_o,
dp_phy_sfp_tx_fault_i => dp_phy_sfp_tx_fault_i,
dp_phy_sfp_los_i => dp_phy_sfp_los_i,
dp_phy_sfp_tx_disable_o => dp_phy_sfp_tx_disable_o,
dp_txtsu_port_id_o => dp_timestamps_o.port_id(4 downto 0),
dp_txtsu_frame_id_o => dp_timestamps_o.frame_id,
dp_txtsu_ts_value_o => dp_timestamps_o.tsval,
dp_txtsu_ts_incorrect_o => dp_timestamps_o.incorrect,
dp_txtsu_stb_o => dp_timestamps_o.stb,
dp_txtsu_ack_i => dp_timestamps_ack_i,
dp_fc_tx_pause_req_i => dp_fc_tx_pause_req_i,
dp_fc_tx_pause_delay_i => dp_fc_tx_pause_delay_i,
dp_fc_tx_pause_ready_o => dp_fc_tx_pause_ready_o
);
timestamps_o.port_id(5) <= '0';
dp_timestamps_o.port_id(5) <= '0';
wrf_snk_o.rty <= '0';
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment