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White Rabbit core collection
Commit 3a074922 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrcore_v2: added missing clk_dmtd_i connection for xwr_endpoint

parent 74635e65
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Showing with 3 additions and 2 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 3a074922
...@@ -24,7 +24,7 @@ package endpoint_pkg is ...@@ -24,7 +24,7 @@ package endpoint_pkg is
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic := '0'; clk_dmtd_i : in std_logic := '0';
rst_n_i : in std_logic; rst_n_i : in std_logic;
pps_csync_p1_i : in std_logic := '0'; pps_csync_p1_i : in std_logic := '0';
phy_rst_o : out std_logic; phy_rst_o : out std_logic;
...@@ -112,7 +112,7 @@ package endpoint_pkg is ...@@ -112,7 +112,7 @@ package endpoint_pkg is
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
clk_dmtd_i: in std_logic := '0'; clk_dmtd_i : in std_logic := '0';
rst_n_i : in std_logic; rst_n_i : in std_logic;
pps_csync_p1_i : in std_logic := '0'; pps_csync_p1_i : in std_logic := '0';
phy_rst_o : out std_logic; phy_rst_o : out std_logic;
......
modules/wrc_core/wr_core.vhd
View file @ 3a074922
...@@ -435,6 +435,7 @@ begin ...@@ -435,6 +435,7 @@ begin
port map ( port map (
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
rst_n_i => rst_net_n, rst_n_i => rst_net_n,
pps_csync_p1_i => s_pps_csync, pps_csync_p1_i => s_pps_csync,
......
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