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White Rabbit core collection
Commit 3ecba0bf authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wr_core: add syscon register with hw board name for SNMP 

wrpc-sw binaries compiled from commit:
a2dd8bb9: spec_defconfig: remove spaces from built-in init script
parent 8bc0d374
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Showing with 37871 additions and 37813 deletions
bin/wrpc/wrc_phy8.bram
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bin/wrpc/wrc_phy8.mif
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bin/wrpc/wrc_phy8_sim.bram
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bin/wrpc/wrc_phy8_sim.mif
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board/common/wr_board_pkg.vhd
View file @ 3ecba0bf
...@@ -63,6 +63,7 @@ package wr_board_pkg is ...@@ -63,6 +63,7 @@ package wr_board_pkg is
generic ( generic (
g_simulation : integer := 0; g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE; g_with_external_clock_input : boolean := TRUE;
g_board_name : string := "NA ";
g_phys_uart : boolean := TRUE; g_phys_uart : boolean := TRUE;
g_virtual_uart : boolean := TRUE; g_virtual_uart : boolean := TRUE;
g_aux_clks : integer := 0; g_aux_clks : integer := 0;
......
board/common/xwrc_board_common.vhd
View file @ 3ecba0bf
...@@ -53,6 +53,7 @@ entity xwrc_board_common is ...@@ -53,6 +53,7 @@ entity xwrc_board_common is
generic( generic(
g_simulation : integer := 0; g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE; g_with_external_clock_input : boolean := TRUE;
g_board_name : string := "NA ";
g_phys_uart : boolean := TRUE; g_phys_uart : boolean := TRUE;
g_virtual_uart : boolean := TRUE; g_virtual_uart : boolean := TRUE;
g_aux_clks : integer := 0; g_aux_clks : integer := 0;
...@@ -320,6 +321,7 @@ begin -- architecture struct ...@@ -320,6 +321,7 @@ begin -- architecture struct
generic map ( generic map (
g_simulation => g_simulation, g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input, g_with_external_clock_input => g_with_external_clock_input,
g_board_name => g_board_name,
g_phys_uart => g_phys_uart, g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart, g_virtual_uart => g_virtual_uart,
g_aux_clks => g_aux_clks, g_aux_clks => g_aux_clks,
......
board/spec/xwrc_board_spec.vhd
View file @ 3ecba0bf
...@@ -416,6 +416,7 @@ begin -- architecture struct ...@@ -416,6 +416,7 @@ begin -- architecture struct
generic map ( generic map (
g_simulation => g_simulation, g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input, g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "SPEC",
g_phys_uart => TRUE, g_phys_uart => TRUE,
g_virtual_uart => TRUE, g_virtual_uart => TRUE,
g_aux_clks => g_aux_clks, g_aux_clks => g_aux_clks,
......
board/svec/xwrc_board_svec.vhd
View file @ 3ecba0bf
...@@ -422,6 +422,7 @@ begin -- architecture struct ...@@ -422,6 +422,7 @@ begin -- architecture struct
generic map ( generic map (
g_simulation => g_simulation, g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input, g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "SVEC",
g_phys_uart => TRUE, g_phys_uart => TRUE,
g_virtual_uart => TRUE, g_virtual_uart => TRUE,
g_aux_clks => g_aux_clks, g_aux_clks => g_aux_clks,
......
board/vfchd/xwrc_board_vfchd.vhd
View file @ 3ecba0bf
...@@ -407,6 +407,7 @@ begin -- architecture struct ...@@ -407,6 +407,7 @@ begin -- architecture struct
generic map ( generic map (
g_simulation => g_simulation, g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input, g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "VFC ",
-- temporary, without it vuart receives but is not able to transmit -- temporary, without it vuart receives but is not able to transmit
g_phys_uart => TRUE, g_phys_uart => TRUE,
g_virtual_uart => TRUE, g_virtual_uart => TRUE,
......
modules/wrc_core/wr_core.vhd
View file @ 3ecba0bf
...@@ -85,6 +85,7 @@ entity wr_core is ...@@ -85,6 +85,7 @@ entity wr_core is
g_simulation : integer := 0; g_simulation : integer := 0;
g_with_external_clock_input : boolean := true; g_with_external_clock_input : boolean := true;
-- --
g_board_name : string := "NA ";
g_phys_uart : boolean := true; g_phys_uart : boolean := true;
g_virtual_uart : boolean := true; g_virtual_uart : boolean := true;
g_aux_clks : integer := 0; g_aux_clks : integer := 0;
...@@ -880,6 +881,7 @@ begin ...@@ -880,6 +881,7 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
PERIPH : wrc_periph PERIPH : wrc_periph
generic map( generic map(
g_board_name => g_board_name,
g_phys_uart => g_phys_uart, g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart, g_virtual_uart => g_virtual_uart,
g_mem_words => g_dpram_size, g_mem_words => g_dpram_size,
......
modules/wrc_core/wrc_diags_pkg.vhd
View file @ 3ecba0bf
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wrc_diags_pkg.vhd -- File : wrc_diags_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_diags_wb.wb -- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
-- Created : Tue Jun 20 09:59:03 2017 -- Created : Mon Jul 3 13:40:08 2017
-- Version : 0x00000001 -- Version : 0x00000001
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -97,10 +97,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is ...@@ -97,10 +97,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0); variable tmp: std_logic_vector(x'length-1 downto 0);
begin begin
for i in 0 to x'length-1 loop for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then if x(i) = '1' then
tmp(i):= '0'; tmp(i):= '1';
else else
tmp(i):=x(i); tmp(i):= '0';
end if; end if;
end loop; end loop;
return tmp; return tmp;
......
modules/wrc_core/wrc_periph.vhd
View file @ 3ecba0bf
...@@ -34,6 +34,7 @@ use work.wrc_diags_wbgen2_pkg.all; ...@@ -34,6 +34,7 @@ use work.wrc_diags_wbgen2_pkg.all;
entity wrc_periph is entity wrc_periph is
generic( generic(
g_board_name : string := "NA ";
g_phys_uart : boolean := true; g_phys_uart : boolean := true;
g_virtual_uart : boolean := false; g_virtual_uart : boolean := false;
g_cntr_period : integer := 62500; g_cntr_period : integer := 62500;
...@@ -97,6 +98,18 @@ architecture struct of wrc_periph is ...@@ -97,6 +98,18 @@ architecture struct of wrc_periph is
-- /16 -1 - to get size in format of MEMSIZE@sysc_hwfr register -- /16 -1 - to get size in format of MEMSIZE@sysc_hwfr register
end f_cnt_memsize; end f_cnt_memsize;
function f_board_name_conv(name : string) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0);
begin
assert (name'length= 4)
report "Board name has to be exactly 4 letters string" severity failure;
ret(31 downto 24) := std_logic_vector(to_unsigned(character'pos(name(1)), 8));
ret(23 downto 16) := std_logic_vector(to_unsigned(character'pos(name(2)), 8));
ret(15 downto 8) := std_logic_vector(to_unsigned(character'pos(name(3)), 8));
ret( 7 downto 0) := std_logic_vector(to_unsigned(character'pos(name(4)), 8));
return ret;
end f_board_name_conv;
signal sysc_regs_i : t_sysc_in_registers; signal sysc_regs_i : t_sysc_in_registers;
signal sysc_regs_o : t_sysc_out_registers; signal sysc_regs_o : t_sysc_out_registers;
...@@ -163,6 +176,11 @@ begin ...@@ -163,6 +176,11 @@ begin
------------------------------------- -------------------------------------
sysc_regs_i.hwfr_memsize_i(3 downto 0) <= f_cnt_memsize(g_mem_words); sysc_regs_i.hwfr_memsize_i(3 downto 0) <= f_cnt_memsize(g_mem_words);
-------------------------------------
-- BOARD NAME
-------------------------------------
sysc_regs_i.hwir_name_i <= f_board_name_conv(g_board_name);
------------------------------------- -------------------------------------
-- TIMER -- TIMER
------------------------------------- -------------------------------------
......
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ 3ecba0bf
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd -- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb -- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Tue Apr 25 12:14:41 2017 -- Created : Mon Jul 3 13:40:08 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...@@ -32,6 +32,7 @@ package sysc_wbgen2_pkg is ...@@ -32,6 +32,7 @@ package sysc_wbgen2_pkg is
gpsr_spi_mosi_i : std_logic; gpsr_spi_mosi_i : std_logic;
gpsr_spi_miso_i : std_logic; gpsr_spi_miso_i : std_logic;
hwfr_memsize_i : std_logic_vector(3 downto 0); hwfr_memsize_i : std_logic_vector(3 downto 0);
hwir_name_i : std_logic_vector(31 downto 0);
tcr_tdiv_i : std_logic_vector(11 downto 0); tcr_tdiv_i : std_logic_vector(11 downto 0);
tvr_i : std_logic_vector(31 downto 0); tvr_i : std_logic_vector(31 downto 0);
diag_info_ver_i : std_logic_vector(15 downto 0); diag_info_ver_i : std_logic_vector(15 downto 0);
...@@ -56,6 +57,7 @@ package sysc_wbgen2_pkg is ...@@ -56,6 +57,7 @@ package sysc_wbgen2_pkg is
gpsr_spi_mosi_i => '0', gpsr_spi_mosi_i => '0',
gpsr_spi_miso_i => '0', gpsr_spi_miso_i => '0',
hwfr_memsize_i => (others => '0'), hwfr_memsize_i => (others => '0'),
hwir_name_i => (others => '0'),
tcr_tdiv_i => (others => '0'), tcr_tdiv_i => (others => '0'),
tvr_i => (others => '0'), tvr_i => (others => '0'),
diag_info_ver_i => (others => '0'), diag_info_ver_i => (others => '0'),
...@@ -204,10 +206,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is ...@@ -204,10 +206,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0); variable tmp: std_logic_vector(x'length-1 downto 0);
begin begin
for i in 0 to x'length-1 loop for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then if x(i) = '1' then
tmp(i):= '0'; tmp(i):= '1';
else else
tmp(i):=x(i); tmp(i):= '0';
end if; end if;
end loop; end loop;
return tmp; return tmp;
...@@ -227,6 +229,7 @@ tmp.gpsr_spi_ncs_i := f_x_to_zero(left.gpsr_spi_ncs_i) or f_x_to_zero(right.gpsr ...@@ -227,6 +229,7 @@ tmp.gpsr_spi_ncs_i := f_x_to_zero(left.gpsr_spi_ncs_i) or f_x_to_zero(right.gpsr
tmp.gpsr_spi_mosi_i := f_x_to_zero(left.gpsr_spi_mosi_i) or f_x_to_zero(right.gpsr_spi_mosi_i); tmp.gpsr_spi_mosi_i := f_x_to_zero(left.gpsr_spi_mosi_i) or f_x_to_zero(right.gpsr_spi_mosi_i);
tmp.gpsr_spi_miso_i := f_x_to_zero(left.gpsr_spi_miso_i) or f_x_to_zero(right.gpsr_spi_miso_i); tmp.gpsr_spi_miso_i := f_x_to_zero(left.gpsr_spi_miso_i) or f_x_to_zero(right.gpsr_spi_miso_i);
tmp.hwfr_memsize_i := f_x_to_zero(left.hwfr_memsize_i) or f_x_to_zero(right.hwfr_memsize_i); tmp.hwfr_memsize_i := f_x_to_zero(left.hwfr_memsize_i) or f_x_to_zero(right.hwfr_memsize_i);
tmp.hwir_name_i := f_x_to_zero(left.hwir_name_i) or f_x_to_zero(right.hwir_name_i);
tmp.tcr_tdiv_i := f_x_to_zero(left.tcr_tdiv_i) or f_x_to_zero(right.tcr_tdiv_i); tmp.tcr_tdiv_i := f_x_to_zero(left.tcr_tdiv_i) or f_x_to_zero(right.tcr_tdiv_i);
tmp.tvr_i := f_x_to_zero(left.tvr_i) or f_x_to_zero(right.tvr_i); tmp.tvr_i := f_x_to_zero(left.tvr_i) or f_x_to_zero(right.tvr_i);
tmp.diag_info_ver_i := f_x_to_zero(left.diag_info_ver_i) or f_x_to_zero(right.diag_info_ver_i); tmp.diag_info_ver_i := f_x_to_zero(left.diag_info_ver_i) or f_x_to_zero(right.diag_info_ver_i);
......
modules/wrc_core/wrc_syscon_regs.h
View file @ 3ecba0bf
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h * File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb * Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Tue Apr 25 12:14:41 2017 * Created : Mon Jul 3 13:40:08 2017
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...@@ -127,6 +127,14 @@ ...@@ -127,6 +127,14 @@
#define SYSC_HWFR_MEMSIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 4) #define SYSC_HWFR_MEMSIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define SYSC_HWFR_MEMSIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 4) #define SYSC_HWFR_MEMSIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for register: Hardware Info Register */
/* definitions for field: Board name in reg: Hardware Info Register */
#define SYSC_HWIR_NAME_MASK WBGEN2_GEN_MASK(0, 32)
#define SYSC_HWIR_NAME_SHIFT 0
#define SYSC_HWIR_NAME_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SYSC_HWIR_NAME_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Timer Control Register */ /* definitions for register: Timer Control Register */
/* definitions for field: Timer Divider in reg: Timer Control Register */ /* definitions for field: Timer Divider in reg: Timer Control Register */
...@@ -259,54 +267,56 @@ ...@@ -259,54 +267,56 @@
#define SYSC_REG_GPCR 0x00000008 #define SYSC_REG_GPCR 0x00000008
/* [0xc]: REG Hardware Feature Register */ /* [0xc]: REG Hardware Feature Register */
#define SYSC_REG_HWFR 0x0000000c #define SYSC_REG_HWFR 0x0000000c
/* [0x10]: REG Timer Control Register */ /* [0x10]: REG Hardware Info Register */
#define SYSC_REG_TCR 0x00000010 #define SYSC_REG_HWIR 0x00000010
/* [0x14]: REG Timer Counter Value Register */ /* [0x14]: REG Timer Control Register */
#define SYSC_REG_TVR 0x00000014 #define SYSC_REG_TCR 0x00000014
/* [0x18]: REG User Diag: version register */ /* [0x18]: REG Timer Counter Value Register */
#define SYSC_REG_DIAG_INFO 0x00000018 #define SYSC_REG_TVR 0x00000018
/* [0x1c]: REG User Diag: number of words */ /* [0x1c]: REG User Diag: version register */
#define SYSC_REG_DIAG_NW 0x0000001c #define SYSC_REG_DIAG_INFO 0x0000001c
/* [0x20]: REG User Diag: Control Register */ /* [0x20]: REG User Diag: number of words */
#define SYSC_REG_DIAG_CR 0x00000020 #define SYSC_REG_DIAG_NW 0x00000020
/* [0x24]: REG User Diag: data to read/write */ /* [0x24]: REG User Diag: Control Register */
#define SYSC_REG_DIAG_DAT 0x00000024 #define SYSC_REG_DIAG_CR 0x00000024
/* [0x28]: REG WRPC Diag: ctrl */ /* [0x28]: REG User Diag: data to read/write */
#define SYSC_REG_WDIAG_CTRL 0x00000028 #define SYSC_REG_DIAG_DAT 0x00000028
/* [0x2c]: REG WRPC Diag: servo status */ /* [0x2c]: REG WRPC Diag: ctrl */
#define SYSC_REG_WDIAG_SSTAT 0x0000002c #define SYSC_REG_WDIAG_CTRL 0x0000002c
/* [0x30]: REG WRPC Diag: Port status */ /* [0x30]: REG WRPC Diag: servo status */
#define SYSC_REG_WDIAG_PSTAT 0x00000030 #define SYSC_REG_WDIAG_SSTAT 0x00000030
/* [0x34]: REG WRPC Diag: PTP state */ /* [0x34]: REG WRPC Diag: Port status */
#define SYSC_REG_WDIAG_PTPSTAT 0x00000034 #define SYSC_REG_WDIAG_PSTAT 0x00000034
/* [0x38]: REG WRPC Diag: AUX state */ /* [0x38]: REG WRPC Diag: PTP state */
#define SYSC_REG_WDIAG_ASTAT 0x00000038 #define SYSC_REG_WDIAG_PTPSTAT 0x00000038
/* [0x3c]: REG WRPC Diag: Tx PTP Frame cnts */ /* [0x3c]: REG WRPC Diag: AUX state */
#define SYSC_REG_WDIAG_TXFCNT 0x0000003c #define SYSC_REG_WDIAG_ASTAT 0x0000003c
/* [0x40]: REG WRPC Diag: Rx PTP Frame cnts */ /* [0x40]: REG WRPC Diag: Tx PTP Frame cnts */
#define SYSC_REG_WDIAG_RXFCNT 0x00000040 #define SYSC_REG_WDIAG_TXFCNT 0x00000040
/* [0x44]: REG WRPC Diag:local time [msb of s] */ /* [0x44]: REG WRPC Diag: Rx PTP Frame cnts */
#define SYSC_REG_WDIAG_SEC_MSB 0x00000044 #define SYSC_REG_WDIAG_RXFCNT 0x00000044
/* [0x48]: REG WRPC Diag: local time [lsb of s] */ /* [0x48]: REG WRPC Diag:local time [msb of s] */
#define SYSC_REG_WDIAG_SEC_LSB 0x00000048 #define SYSC_REG_WDIAG_SEC_MSB 0x00000048
/* [0x4c]: REG WRPC Diag: local time [ns] */ /* [0x4c]: REG WRPC Diag: local time [lsb of s] */
#define SYSC_REG_WDIAG_NS 0x0000004c #define SYSC_REG_WDIAG_SEC_LSB 0x0000004c
/* [0x50]: REG WRPC Diag: Round trip (mu) [msb of ps] */ /* [0x50]: REG WRPC Diag: local time [ns] */
#define SYSC_REG_WDIAG_MU_MSB 0x00000050 #define SYSC_REG_WDIAG_NS 0x00000050
/* [0x54]: REG WRPC Diag: Round trip (mu) [lsb of ps] */ /* [0x54]: REG WRPC Diag: Round trip (mu) [msb of ps] */
#define SYSC_REG_WDIAG_MU_LSB 0x00000054 #define SYSC_REG_WDIAG_MU_MSB 0x00000054
/* [0x58]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */ /* [0x58]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
#define SYSC_REG_WDIAG_DMS_MSB 0x00000058 #define SYSC_REG_WDIAG_MU_LSB 0x00000058
/* [0x5c]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */ /* [0x5c]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
#define SYSC_REG_WDIAG_DMS_LSB 0x0000005c #define SYSC_REG_WDIAG_DMS_MSB 0x0000005c
/* [0x60]: REG WRPC Diag: Total link asymmetry [ps] */ /* [0x60]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
#define SYSC_REG_WDIAG_ASYM 0x00000060 #define SYSC_REG_WDIAG_DMS_LSB 0x00000060
/* [0x64]: REG WRPC Diag: Clock offset (cko) [ps] */ /* [0x64]: REG WRPC Diag: Total link asymmetry [ps] */
#define SYSC_REG_WDIAG_CKO 0x00000064 #define SYSC_REG_WDIAG_ASYM 0x00000064
/* [0x68]: REG WRPC Diag: Phase setpoint (setp) [ps] */ /* [0x68]: REG WRPC Diag: Clock offset (cko) [ps] */
#define SYSC_REG_WDIAG_SETP 0x00000068 #define SYSC_REG_WDIAG_CKO 0x00000068
/* [0x6c]: REG WRPC Diag: Update counter (ucnt) */ /* [0x6c]: REG WRPC Diag: Phase setpoint (setp) [ps] */
#define SYSC_REG_WDIAG_UCNT 0x0000006c #define SYSC_REG_WDIAG_SETP 0x0000006c
/* [0x70]: REG WRPC Diag: Board temperature [C degree] */ /* [0x70]: REG WRPC Diag: Update counter (ucnt) */
#define SYSC_REG_WDIAG_TEMP 0x00000070 #define SYSC_REG_WDIAG_UCNT 0x00000070
/* [0x74]: REG WRPC Diag: Board temperature [C degree] */
#define SYSC_REG_WDIAG_TEMP 0x00000074
#endif #endif
modules/wrc_core/wrc_syscon_wb.vhd
View file @ 3ecba0bf
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd -- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb -- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Tue Apr 25 12:14:41 2017 -- Created : Mon Jul 3 13:40:08 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...@@ -88,22 +88,12 @@ signal sysc_wdiag_temp_int : std_logic_vector(31 downto 0); ...@@ -88,22 +88,12 @@ signal sysc_wdiag_temp_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0); signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ; signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards. -- Some internal signals assignments
wrdata_reg <= wb_dat_i; wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
-- --
-- Main register bank access process. -- Main register bank access process.
process (clk_sys_i, rst_n_i) process (clk_sys_i, rst_n_i)
...@@ -378,6 +368,12 @@ begin ...@@ -378,6 +368,12 @@ begin
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00100" => when "00100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.hwir_name_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_tcr_enable_int <= wrdata_reg(31); sysc_tcr_enable_int <= wrdata_reg(31);
end if; end if;
...@@ -404,27 +400,27 @@ begin ...@@ -404,27 +400,27 @@ begin
rddata_reg(30) <= 'X'; rddata_reg(30) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00101" => when "00110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(31 downto 0) <= regs_i.tvr_i; rddata_reg(31 downto 0) <= regs_i.tvr_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00110" => when "00111" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(15 downto 0) <= regs_i.diag_info_ver_i; rddata_reg(15 downto 0) <= regs_i.diag_info_ver_i;
rddata_reg(31 downto 16) <= regs_i.diag_info_id_i; rddata_reg(31 downto 16) <= regs_i.diag_info_id_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00111" => when "01000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(15 downto 0) <= regs_i.diag_nw_rw_i; rddata_reg(15 downto 0) <= regs_i.diag_nw_rw_i;
rddata_reg(31 downto 16) <= regs_i.diag_nw_ro_i; rddata_reg(31 downto 16) <= regs_i.diag_nw_ro_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01000" => when "01001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
regs_o.diag_cr_adr_load_o <= '1'; regs_o.diag_cr_adr_load_o <= '1';
sysc_diag_cr_rw_int <= wrdata_reg(31); sysc_diag_cr_rw_int <= wrdata_reg(31);
...@@ -448,14 +444,14 @@ begin ...@@ -448,14 +444,14 @@ begin
rddata_reg(30) <= 'X'; rddata_reg(30) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01001" => when "01010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
regs_o.diag_dat_load_o <= '1'; regs_o.diag_dat_load_o <= '1';
end if; end if;
rddata_reg(31 downto 0) <= regs_i.diag_dat_i; rddata_reg(31 downto 0) <= regs_i.diag_dat_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01010" => when "01011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_ctrl_data_valid_int <= wrdata_reg(0); sysc_wdiag_ctrl_data_valid_int <= wrdata_reg(0);
end if; end if;
...@@ -493,7 +489,7 @@ begin ...@@ -493,7 +489,7 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01011" => when "01100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_sstat_wr_mode_int <= wrdata_reg(0); sysc_wdiag_sstat_wr_mode_int <= wrdata_reg(0);
sysc_wdiag_sstat_servostate_int <= wrdata_reg(11 downto 8); sysc_wdiag_sstat_servostate_int <= wrdata_reg(11 downto 8);
...@@ -529,7 +525,7 @@ begin ...@@ -529,7 +525,7 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01100" => when "01101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_pstat_link_int <= wrdata_reg(0); sysc_wdiag_pstat_link_int <= wrdata_reg(0);
sysc_wdiag_pstat_locked_int <= wrdata_reg(1); sysc_wdiag_pstat_locked_int <= wrdata_reg(1);
...@@ -568,7 +564,7 @@ begin ...@@ -568,7 +564,7 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01101" => when "01110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_ptpstat_ptpstate_int <= wrdata_reg(7 downto 0); sysc_wdiag_ptpstat_ptpstate_int <= wrdata_reg(7 downto 0);
end if; end if;
...@@ -599,7 +595,7 @@ begin ...@@ -599,7 +595,7 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01110" => when "01111" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_astat_aux_int <= wrdata_reg(7 downto 0); sysc_wdiag_astat_aux_int <= wrdata_reg(7 downto 0);
end if; end if;
...@@ -630,98 +626,98 @@ begin ...@@ -630,98 +626,98 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "01111" => when "10000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_txfcnt_int <= wrdata_reg(31 downto 0); sysc_wdiag_txfcnt_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_txfcnt_int; rddata_reg(31 downto 0) <= sysc_wdiag_txfcnt_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10000" => when "10001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_rxfcnt_int <= wrdata_reg(31 downto 0); sysc_wdiag_rxfcnt_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_rxfcnt_int; rddata_reg(31 downto 0) <= sysc_wdiag_rxfcnt_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10001" => when "10010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_sec_msb_int <= wrdata_reg(31 downto 0); sysc_wdiag_sec_msb_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_sec_msb_int; rddata_reg(31 downto 0) <= sysc_wdiag_sec_msb_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10010" => when "10011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_sec_lsb_int <= wrdata_reg(31 downto 0); sysc_wdiag_sec_lsb_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_sec_lsb_int; rddata_reg(31 downto 0) <= sysc_wdiag_sec_lsb_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10011" => when "10100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_ns_int <= wrdata_reg(31 downto 0); sysc_wdiag_ns_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_ns_int; rddata_reg(31 downto 0) <= sysc_wdiag_ns_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10100" => when "10101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_mu_msb_int <= wrdata_reg(31 downto 0); sysc_wdiag_mu_msb_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_mu_msb_int; rddata_reg(31 downto 0) <= sysc_wdiag_mu_msb_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10101" => when "10110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_mu_lsb_int <= wrdata_reg(31 downto 0); sysc_wdiag_mu_lsb_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_mu_lsb_int; rddata_reg(31 downto 0) <= sysc_wdiag_mu_lsb_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10110" => when "10111" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_dms_msb_int <= wrdata_reg(31 downto 0); sysc_wdiag_dms_msb_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_dms_msb_int; rddata_reg(31 downto 0) <= sysc_wdiag_dms_msb_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10111" => when "11000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_dms_lsb_int <= wrdata_reg(31 downto 0); sysc_wdiag_dms_lsb_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_dms_lsb_int; rddata_reg(31 downto 0) <= sysc_wdiag_dms_lsb_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11000" => when "11001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_asym_int <= wrdata_reg(31 downto 0); sysc_wdiag_asym_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_asym_int; rddata_reg(31 downto 0) <= sysc_wdiag_asym_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11001" => when "11010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_cko_int <= wrdata_reg(31 downto 0); sysc_wdiag_cko_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_cko_int; rddata_reg(31 downto 0) <= sysc_wdiag_cko_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11010" => when "11011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_setp_int <= wrdata_reg(31 downto 0); sysc_wdiag_setp_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_setp_int; rddata_reg(31 downto 0) <= sysc_wdiag_setp_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11011" => when "11100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_ucnt_int <= wrdata_reg(31 downto 0); sysc_wdiag_ucnt_int <= wrdata_reg(31 downto 0);
end if; end if;
rddata_reg(31 downto 0) <= sysc_wdiag_ucnt_int; rddata_reg(31 downto 0) <= sysc_wdiag_ucnt_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11100" => when "11101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
sysc_wdiag_temp_int <= wrdata_reg(31 downto 0); sysc_wdiag_temp_int <= wrdata_reg(31 downto 0);
end if; end if;
...@@ -921,6 +917,7 @@ begin ...@@ -921,6 +917,7 @@ begin
-- Memory size -- Memory size
-- Board name
-- Timer Divider -- Timer Divider
-- Timer Enable -- Timer Enable
regs_o.tcr_enable_o <= sysc_tcr_enable_int; regs_o.tcr_enable_o <= sysc_tcr_enable_int;
......
modules/wrc_core/wrc_syscon_wb.wb
View file @ 3ecba0bf
...@@ -269,6 +269,20 @@ peripheral { ...@@ -269,6 +269,20 @@ peripheral {
}; };
reg {
name = "Hardware Info Register";
prefix = "HWIR";
field {
name = "Board name";
prefix = "NAME";
size = 32;
description = "4-letter name of the board";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg { reg {
name = "Timer Control Register"; name = "Timer Control Register";
prefix = "TCR"; prefix = "TCR";
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 3ecba0bf
...@@ -225,6 +225,7 @@ package wrcore_pkg is ...@@ -225,6 +225,7 @@ package wrcore_pkg is
component wrc_periph is component wrc_periph is
generic( generic(
g_board_name : string := "NA ";
g_phys_uart : boolean := true; g_phys_uart : boolean := true;
g_virtual_uart : boolean := false; g_virtual_uart : boolean := false;
g_cntr_period : integer := 62500; g_cntr_period : integer := 62500;
...@@ -340,6 +341,7 @@ package wrcore_pkg is ...@@ -340,6 +341,7 @@ package wrcore_pkg is
component xwr_core is component xwr_core is
generic( generic(
g_simulation : integer := 0; g_simulation : integer := 0;
g_board_name : string := "NA ";
g_phys_uart : boolean := true; g_phys_uart : boolean := true;
g_virtual_uart : boolean := true; g_virtual_uart : boolean := true;
g_with_external_clock_input : boolean := true; g_with_external_clock_input : boolean := true;
...@@ -479,6 +481,7 @@ package wrcore_pkg is ...@@ -479,6 +481,7 @@ package wrcore_pkg is
g_simulation : integer := 0; g_simulation : integer := 0;
g_with_external_clock_input : boolean := true; g_with_external_clock_input : boolean := true;
-- --
g_board_name : string := "NA ";
g_phys_uart : boolean := true; g_phys_uart : boolean := true;
g_virtual_uart : boolean := true; g_virtual_uart : boolean := true;
g_aux_clks : integer := 0; g_aux_clks : integer := 0;
......
modules/wrc_core/xwr_core.vhd
View file @ 3ecba0bf
...@@ -69,6 +69,7 @@ entity xwr_core is ...@@ -69,6 +69,7 @@ entity xwr_core is
g_simulation : integer := 0; g_simulation : integer := 0;
g_with_external_clock_input : boolean := true; g_with_external_clock_input : boolean := true;
-- --
g_board_name : string := "NA ";
g_phys_uart : boolean := true; g_phys_uart : boolean := true;
g_virtual_uart : boolean := true; g_virtual_uart : boolean := true;
g_aux_clks : integer := 0; g_aux_clks : integer := 0;
...@@ -264,6 +265,7 @@ begin ...@@ -264,6 +265,7 @@ begin
WRPC : wr_core WRPC : wr_core
generic map( generic map(
g_simulation => g_simulation, g_simulation => g_simulation,
g_board_name => g_board_name,
g_phys_uart => g_phys_uart, g_phys_uart => g_phys_uart,
g_virtual_uart => g_virtual_uart, g_virtual_uart => g_virtual_uart,
g_rx_buffer_size => g_ep_rxbuf_size, g_rx_buffer_size => g_ep_rxbuf_size,
......
sim/wrc_syscon_regs.vh
View file @ 3ecba0bf
...@@ -54,60 +54,63 @@ ...@@ -54,60 +54,63 @@
`define ADDR_SYSC_HWFR 7'hc `define ADDR_SYSC_HWFR 7'hc
`define SYSC_HWFR_MEMSIZE_OFFSET 0 `define SYSC_HWFR_MEMSIZE_OFFSET 0
`define SYSC_HWFR_MEMSIZE 32'h0000000f `define SYSC_HWFR_MEMSIZE 32'h0000000f
`define ADDR_SYSC_TCR 7'h10 `define ADDR_SYSC_HWIR 7'h10
`define SYSC_HWIR_NAME_OFFSET 0
`define SYSC_HWIR_NAME 32'hffffffff
`define ADDR_SYSC_TCR 7'h14
`define SYSC_TCR_TDIV_OFFSET 0 `define SYSC_TCR_TDIV_OFFSET 0
`define SYSC_TCR_TDIV 32'h00000fff `define SYSC_TCR_TDIV 32'h00000fff
`define SYSC_TCR_ENABLE_OFFSET 31 `define SYSC_TCR_ENABLE_OFFSET 31
`define SYSC_TCR_ENABLE 32'h80000000 `define SYSC_TCR_ENABLE 32'h80000000
`define ADDR_SYSC_TVR 7'h14 `define ADDR_SYSC_TVR 7'h18
`define ADDR_SYSC_DIAG_INFO 7'h18 `define ADDR_SYSC_DIAG_INFO 7'h1c
`define SYSC_DIAG_INFO_VER_OFFSET 0 `define SYSC_DIAG_INFO_VER_OFFSET 0
`define SYSC_DIAG_INFO_VER 32'h0000ffff `define SYSC_DIAG_INFO_VER 32'h0000ffff
`define SYSC_DIAG_INFO_ID_OFFSET 16 `define SYSC_DIAG_INFO_ID_OFFSET 16
`define SYSC_DIAG_INFO_ID 32'hffff0000 `define SYSC_DIAG_INFO_ID 32'hffff0000
`define ADDR_SYSC_DIAG_NW 7'h1c `define ADDR_SYSC_DIAG_NW 7'h20
`define SYSC_DIAG_NW_RW_OFFSET 0 `define SYSC_DIAG_NW_RW_OFFSET 0
`define SYSC_DIAG_NW_RW 32'h0000ffff `define SYSC_DIAG_NW_RW 32'h0000ffff
`define SYSC_DIAG_NW_RO_OFFSET 16 `define SYSC_DIAG_NW_RO_OFFSET 16
`define SYSC_DIAG_NW_RO 32'hffff0000 `define SYSC_DIAG_NW_RO 32'hffff0000
`define ADDR_SYSC_DIAG_CR 7'h20 `define ADDR_SYSC_DIAG_CR 7'h24
`define SYSC_DIAG_CR_ADR_OFFSET 0 `define SYSC_DIAG_CR_ADR_OFFSET 0
`define SYSC_DIAG_CR_ADR 32'h0000ffff `define SYSC_DIAG_CR_ADR 32'h0000ffff
`define SYSC_DIAG_CR_RW_OFFSET 31 `define SYSC_DIAG_CR_RW_OFFSET 31
`define SYSC_DIAG_CR_RW 32'h80000000 `define SYSC_DIAG_CR_RW 32'h80000000
`define ADDR_SYSC_DIAG_DAT 7'h24 `define ADDR_SYSC_DIAG_DAT 7'h28
`define ADDR_SYSC_WDIAG_CTRL 7'h28 `define ADDR_SYSC_WDIAG_CTRL 7'h2c
`define SYSC_WDIAG_CTRL_DATA_VALID_OFFSET 0 `define SYSC_WDIAG_CTRL_DATA_VALID_OFFSET 0
`define SYSC_WDIAG_CTRL_DATA_VALID 32'h00000001 `define SYSC_WDIAG_CTRL_DATA_VALID 32'h00000001
`define SYSC_WDIAG_CTRL_DATA_SNAPSHOT_OFFSET 8 `define SYSC_WDIAG_CTRL_DATA_SNAPSHOT_OFFSET 8
`define SYSC_WDIAG_CTRL_DATA_SNAPSHOT 32'h00000100 `define SYSC_WDIAG_CTRL_DATA_SNAPSHOT 32'h00000100
`define ADDR_SYSC_WDIAG_SSTAT 7'h2c `define ADDR_SYSC_WDIAG_SSTAT 7'h30
`define SYSC_WDIAG_SSTAT_WR_MODE_OFFSET 0 `define SYSC_WDIAG_SSTAT_WR_MODE_OFFSET 0
`define SYSC_WDIAG_SSTAT_WR_MODE 32'h00000001 `define SYSC_WDIAG_SSTAT_WR_MODE 32'h00000001
`define SYSC_WDIAG_SSTAT_SERVOSTATE_OFFSET 8 `define SYSC_WDIAG_SSTAT_SERVOSTATE_OFFSET 8
`define SYSC_WDIAG_SSTAT_SERVOSTATE 32'h00000f00 `define SYSC_WDIAG_SSTAT_SERVOSTATE 32'h00000f00
`define ADDR_SYSC_WDIAG_PSTAT 7'h30 `define ADDR_SYSC_WDIAG_PSTAT 7'h34
`define SYSC_WDIAG_PSTAT_LINK_OFFSET 0 `define SYSC_WDIAG_PSTAT_LINK_OFFSET 0
`define SYSC_WDIAG_PSTAT_LINK 32'h00000001 `define SYSC_WDIAG_PSTAT_LINK 32'h00000001
`define SYSC_WDIAG_PSTAT_LOCKED_OFFSET 1 `define SYSC_WDIAG_PSTAT_LOCKED_OFFSET 1
`define SYSC_WDIAG_PSTAT_LOCKED 32'h00000002 `define SYSC_WDIAG_PSTAT_LOCKED 32'h00000002
`define ADDR_SYSC_WDIAG_PTPSTAT 7'h34 `define ADDR_SYSC_WDIAG_PTPSTAT 7'h38
`define SYSC_WDIAG_PTPSTAT_PTPSTATE_OFFSET 0 `define SYSC_WDIAG_PTPSTAT_PTPSTATE_OFFSET 0
`define SYSC_WDIAG_PTPSTAT_PTPSTATE 32'h000000ff `define SYSC_WDIAG_PTPSTAT_PTPSTATE 32'h000000ff
`define ADDR_SYSC_WDIAG_ASTAT 7'h38 `define ADDR_SYSC_WDIAG_ASTAT 7'h3c
`define SYSC_WDIAG_ASTAT_AUX_OFFSET 0 `define SYSC_WDIAG_ASTAT_AUX_OFFSET 0
`define SYSC_WDIAG_ASTAT_AUX 32'h000000ff `define SYSC_WDIAG_ASTAT_AUX 32'h000000ff
`define ADDR_SYSC_WDIAG_TXFCNT 7'h3c `define ADDR_SYSC_WDIAG_TXFCNT 7'h40
`define ADDR_SYSC_WDIAG_RXFCNT 7'h40 `define ADDR_SYSC_WDIAG_RXFCNT 7'h44
`define ADDR_SYSC_WDIAG_SEC_MSB 7'h44 `define ADDR_SYSC_WDIAG_SEC_MSB 7'h48
`define ADDR_SYSC_WDIAG_SEC_LSB 7'h48 `define ADDR_SYSC_WDIAG_SEC_LSB 7'h4c
`define ADDR_SYSC_WDIAG_NS 7'h4c `define ADDR_SYSC_WDIAG_NS 7'h50
`define ADDR_SYSC_WDIAG_MU_MSB 7'h50 `define ADDR_SYSC_WDIAG_MU_MSB 7'h54
`define ADDR_SYSC_WDIAG_MU_LSB 7'h54 `define ADDR_SYSC_WDIAG_MU_LSB 7'h58
`define ADDR_SYSC_WDIAG_DMS_MSB 7'h58 `define ADDR_SYSC_WDIAG_DMS_MSB 7'h5c
`define ADDR_SYSC_WDIAG_DMS_LSB 7'h5c `define ADDR_SYSC_WDIAG_DMS_LSB 7'h60
`define ADDR_SYSC_WDIAG_ASYM 7'h60 `define ADDR_SYSC_WDIAG_ASYM 7'h64
`define ADDR_SYSC_WDIAG_CKO 7'h64 `define ADDR_SYSC_WDIAG_CKO 7'h68
`define ADDR_SYSC_WDIAG_SETP 7'h68 `define ADDR_SYSC_WDIAG_SETP 7'h6c
`define ADDR_SYSC_WDIAG_UCNT 7'h6c `define ADDR_SYSC_WDIAG_UCNT 7'h70
`define ADDR_SYSC_WDIAG_TEMP 7'h70 `define ADDR_SYSC_WDIAG_TEMP 7'h74
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