pps_gen: little changes in signal names

422fe764 · Grzegorz Daniluk · c60fdf6c · 422fe764 · 422fe764 · 422fe764
Commit 422fe764 authored Oct 27, 2011 by Grzegorz Daniluk
5 changed files
--- a/modules/wrsw_pps_gen/pps_gen_regs.h
+++ b/modules/wrsw_pps_gen/pps_gen_regs.h
@@ -3,7 +3,7 @@
  * File           : pps_gen_regs.h
  * Author         : auto-generated by wbgen2 from wrsw_pps_gen.wb
-  * Created        : Thu Oct 27 00:59:03 2011
+  * Created        : Thu Oct 27 21:29:19 2011
  * Standard       : ANSI C
    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
@@ -69,10 +69,10 @@
 #define PPSG_ESCR_SYNC                        WBGEN2_GEN_MASK(0, 1)
 /* definitions for field: PPS output valid in reg: External sync control register */
-#define PPSG_ESCR_PPS_VAL                     WBGEN2_GEN_MASK(1, 1)
+#define PPSG_ESCR_PPS_VALID                   WBGEN2_GEN_MASK(1, 1)
-/* definitions for field: Timecode output(UTC+nanosec) valid in reg: External sync control register */
+/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
-#define PPSG_ESCR_TC_VAL                      WBGEN2_GEN_MASK(2, 1)
+#define PPSG_ESCR_TM_VALID                    WBGEN2_GEN_MASK(2, 1)
 PACKED struct PPSG_WB {
  /* [0x0]: REG Control Register */

--- a/modules/wrsw_pps_gen/pps_gen_wb.vhd
+++ b/modules/wrsw_pps_gen/pps_gen_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : pps_gen_wb.vhd
 -- Author         : auto-generated by wbgen2 from wrsw_pps_gen.wb
-- Created        : Thu Oct 27 00:59:03 2011
+-- Created        : Thu Oct 27 21:29:19 2011
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
@@ -59,9 +59,9 @@ entity pps_gen_wb is
    ppsg_escr_sync_i                         : in     std_logic;
    ppsg_escr_sync_load_o                    : out    std_logic;
 -- Port for asynchronous (clock: refclk_i) BIT field: 'PPS output valid' in reg: 'External sync control register'
-    ppsg_escr_pps_val_o                      : out    std_logic;
+    ppsg_escr_pps_valid_o                    : out    std_logic;
-- Port for asynchronous (clock: refclk_i) BIT field: 'Timecode output(UTC+nanosec) valid' in reg: 'External sync control register'
+-- Port for asynchronous (clock: refclk_i) BIT field: 'Timecode output(UTC+cycles) valid' in reg: 'External sync control register'
-    ppsg_escr_tc_val_o                       : out    std_logic
+    ppsg_escr_tm_valid_o                     : out    std_logic
  );
 end pps_gen_wb;
@@ -125,12 +125,12 @@ signal ppsg_escr_sync_lw_s0                     : std_logic      ;
 signal ppsg_escr_sync_lw_s1                     : std_logic      ;
 signal ppsg_escr_sync_lw_s2                     : std_logic      ;
 signal ppsg_escr_sync_rwsel                     : std_logic      ;
-signal ppsg_escr_pps_val_int                    : std_logic      ;
+signal ppsg_escr_pps_valid_int                  : std_logic      ;
-signal ppsg_escr_pps_val_sync0                  : std_logic      ;
+signal ppsg_escr_pps_valid_sync0                : std_logic      ;
-signal ppsg_escr_pps_val_sync1                  : std_logic      ;
+signal ppsg_escr_pps_valid_sync1                : std_logic      ;
-signal ppsg_escr_tc_val_int                     : std_logic      ;
+signal ppsg_escr_tm_valid_int                   : std_logic      ;
-signal ppsg_escr_tc_val_sync0                   : std_logic      ;
+signal ppsg_escr_tm_valid_sync0                 : std_logic      ;
-signal ppsg_escr_tc_val_sync1                   : std_logic      ;
+signal ppsg_escr_tm_valid_sync1                 : std_logic      ;
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
@@ -190,8 +190,8 @@ begin
      ppsg_escr_sync_lw_read_in_progress <= '0';
      ppsg_escr_sync_rwsel <= '0';
      ppsg_escr_sync_int_write <= '0';
-      ppsg_escr_pps_val_int <= '0';
+      ppsg_escr_pps_valid_int <= '0';
-      ppsg_escr_tc_val_int <= '0';
+      ppsg_escr_tm_valid_int <= '0';
    elsif rising_edge(bus_clock_int) then
 -- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
@@ -458,9 +458,9 @@ begin
              ppsg_escr_sync_lw_delay <= '1';
              ppsg_escr_sync_lw_read_in_progress <= '0';
              ppsg_escr_sync_rwsel <= '1';
-              ppsg_escr_pps_val_int <= wrdata_reg(1);
+              ppsg_escr_pps_valid_int <= wrdata_reg(1);
              rddata_reg(1) <= 'X';
-              ppsg_escr_tc_val_int <= wrdata_reg(2);
+              ppsg_escr_tm_valid_int <= wrdata_reg(2);
              rddata_reg(2) <= 'X';
            else
              rddata_reg(0) <= 'X';
@@ -468,8 +468,8 @@ begin
              ppsg_escr_sync_lw_delay <= '1';
              ppsg_escr_sync_lw_read_in_progress <= '1';
              ppsg_escr_sync_rwsel <= '0';
-              rddata_reg(1) <= ppsg_escr_pps_val_int;
+              rddata_reg(1) <= ppsg_escr_pps_valid_int;
-              rddata_reg(2) <= ppsg_escr_tc_val_int;
+              rddata_reg(2) <= ppsg_escr_tm_valid_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
@@ -719,29 +719,29 @@ begin
  process (refclk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
-      ppsg_escr_pps_val_o <= '0';
+      ppsg_escr_pps_valid_o <= '0';
-      ppsg_escr_pps_val_sync0 <= '0';
+      ppsg_escr_pps_valid_sync0 <= '0';
-      ppsg_escr_pps_val_sync1 <= '0';
+      ppsg_escr_pps_valid_sync1 <= '0';
    elsif rising_edge(refclk_i) then
-      ppsg_escr_pps_val_sync0 <= ppsg_escr_pps_val_int;
+      ppsg_escr_pps_valid_sync0 <= ppsg_escr_pps_valid_int;
-      ppsg_escr_pps_val_sync1 <= ppsg_escr_pps_val_sync0;
+      ppsg_escr_pps_valid_sync1 <= ppsg_escr_pps_valid_sync0;
-      ppsg_escr_pps_val_o <= ppsg_escr_pps_val_sync1;
+      ppsg_escr_pps_valid_o <= ppsg_escr_pps_valid_sync1;
    end if;
  end process;
-- Timecode output(UTC+nanosec) valid
+-- Timecode output(UTC+cycles) valid
-- synchronizer chain for field : Timecode output(UTC+nanosec) valid (type RW/RO, bus_clock_int <-> refclk_i)
+-- synchronizer chain for field : Timecode output(UTC+cycles) valid (type RW/RO, bus_clock_int <-> refclk_i)
  process (refclk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
-      ppsg_escr_tc_val_o <= '0';
+      ppsg_escr_tm_valid_o <= '0';
-      ppsg_escr_tc_val_sync0 <= '0';
+      ppsg_escr_tm_valid_sync0 <= '0';
-      ppsg_escr_tc_val_sync1 <= '0';
+      ppsg_escr_tm_valid_sync1 <= '0';
    elsif rising_edge(refclk_i) then
-      ppsg_escr_tc_val_sync0 <= ppsg_escr_tc_val_int;
+      ppsg_escr_tm_valid_sync0 <= ppsg_escr_tm_valid_int;
-      ppsg_escr_tc_val_sync1 <= ppsg_escr_tc_val_sync0;
+      ppsg_escr_tm_valid_sync1 <= ppsg_escr_tm_valid_sync0;
-      ppsg_escr_tc_val_o <= ppsg_escr_tc_val_sync1;
+      ppsg_escr_tm_valid_o <= ppsg_escr_tm_valid_sync1;
    end if;
  end process;

--- a/modules/wrsw_pps_gen/wrsw_pps_gen.vhd
+++ b/modules/wrsw_pps_gen/wrsw_pps_gen.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-09-02
-- Last update: 2011-10-26
+-- Last update: 2011-10-27
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -38,16 +38,16 @@ entity wrsw_pps_gen is
    clk_ref_i : in std_logic;
    clk_sys_i : in std_logic;
-    rst_n_i   : in std_logic;
+    rst_n_i : in std_logic;
-    wb_addr_i : in  std_logic_vector(3 downto 0);
+    wb_addr_i  : in  std_logic_vector(3 downto 0);
-    wb_data_i : in  std_logic_vector(31 downto 0);
+    wb_data_i  : in  std_logic_vector(31 downto 0);
-    wb_data_o : out std_logic_vector(31 downto 0);
+    wb_data_o  : out std_logic_vector(31 downto 0);
-    wb_cyc_i  : in  std_logic;
+    wb_cyc_i   : in  std_logic;
-    wb_sel_i  : in  std_logic_vector(3 downto 0);
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
-    wb_stb_i  : in  std_logic;
+    wb_stb_i   : in  std_logic;
-    wb_we_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
-    wb_ack_o  : out std_logic;
+    wb_ack_o   : out std_logic;
    wb_stall_o : out std_logic;
    pps_in_i : in std_logic;
@@ -56,10 +56,10 @@ entity wrsw_pps_gen is
    pps_csync_o : out std_logic;
    pps_out_o   : out std_logic;
-    pps_val_o   : out std_logic;
+    pps_valid_o     : out std_logic;
-    tc_utc_o    : out std_logic_vector(39 downto 0);
+    tm_utc_o        : out std_logic_vector(39 downto 0);
-    tc_nsec_o   : out std_logic_vector(27 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
-    tc_val_o    : out std_logic
+    tm_time_valid_o : out std_logic
    );
 end wrsw_pps_gen;
@@ -99,8 +99,8 @@ architecture behavioral of wrsw_pps_gen is
      ppsg_escr_sync_o       : out std_logic;
      ppsg_escr_sync_i       : in  std_logic;
      ppsg_escr_sync_load_o  : out std_logic;
-      ppsg_escr_pps_val_o    : out std_logic;
+      ppsg_escr_pps_valid_o  : out std_logic;
-      ppsg_escr_tc_val_o     : out std_logic);
+      ppsg_escr_tm_valid_o   : out std_logic);
  end component;
@@ -119,17 +119,17 @@ architecture behavioral of wrsw_pps_gen is
  signal ppsg_cntr_utclo : std_logic_vector(31 downto 0);
  signal ppsg_cntr_utchi : std_logic_vector(7 downto 0);
-  signal ppsg_adj_nsec     : std_logic_vector(27 downto 0);
+  signal ppsg_adj_nsec      : std_logic_vector(27 downto 0);
-  signal ppsg_adj_nsec_wr  : std_logic;
+  signal ppsg_adj_nsec_wr   : std_logic;
-  signal ppsg_adj_utclo    : std_logic_vector(31 downto 0);
+  signal ppsg_adj_utclo     : std_logic_vector(31 downto 0);
-  signal ppsg_adj_utclo_wr : std_logic;
+  signal ppsg_adj_utclo_wr  : std_logic;
-  signal ppsg_adj_utchi    : std_logic_vector(7 downto 0);
+  signal ppsg_adj_utchi     : std_logic_vector(7 downto 0);
-  signal ppsg_adj_utchi_wr : std_logic; signal ppsg_escr_sync_load  : std_logic;
+  signal ppsg_adj_utchi_wr  : std_logic; signal ppsg_escr_sync_load : std_logic;
-  signal ppsg_escr_sync_in   : std_logic;
+  signal ppsg_escr_sync_in  : std_logic;
  signal ppsg_escr_sync_out : std_logic;
-  signal ppsg_escr_pps_val : std_logic;
+  signal ppsg_escr_pps_valid : std_logic;
-  signal ppsg_escr_tc_val  : std_logic;
+  signal ppsg_escr_tm_valid  : std_logic;
  signal cntr_nsec : unsigned (27 downto 0);
  signal cntr_utc  : unsigned (39 downto 0);
@@ -155,13 +155,13 @@ architecture behavioral of wrsw_pps_gen is
  signal ext_sync_p       : std_logic;
  signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
-  signal wb_out : t_wishbone_slave_out;
+  signal wb_out       : t_wishbone_slave_out;
-  signal wb_in  : t_wishbone_slave_in;
+  signal wb_in        : t_wishbone_slave_in;
 begin  -- behavioral
-  resized_addr(3 downto 0) <= wb_addr_i;
+  resized_addr(3 downto 0)                          <= wb_addr_i;
-  resized_addr(c_wishbone_address_width-1 downto 4) <= (others=>'0');
+  resized_addr(c_wishbone_address_width-1 downto 4) <= (others => '0');
  U_Adapter : wb_slave_adapter
    generic map (
@@ -350,38 +350,38 @@ begin  -- behavioral
  Uwb_slave : pps_gen_wb
    port map (
-      rst_n_i                 => rst_n_i,
+      rst_n_i                => rst_n_i,
-      wb_clk_i                => clk_sys_i,
+      wb_clk_i               => clk_sys_i,
-      wb_addr_i               => wb_in.adr(2 downto 0),
+      wb_addr_i              => wb_in.adr(2 downto 0),
-      wb_data_i               => wb_in.dat,
+      wb_data_i              => wb_in.dat,
-      wb_data_o               => wb_out.dat,
+      wb_data_o              => wb_out.dat,
-      wb_cyc_i                => wb_in.cyc,
+      wb_cyc_i               => wb_in.cyc,
-      wb_sel_i                => wb_in.sel,
+      wb_sel_i               => wb_in.sel,
-      wb_stb_i                => wb_in.stb,
+      wb_stb_i               => wb_in.stb,
-      wb_we_i                 => wb_in.we,
+      wb_we_i                => wb_in.we,
-      wb_ack_o                => wb_out.ack,
+      wb_ack_o               => wb_out.ack,
-      refclk_i                => clk_ref_i,
+      refclk_i               => clk_ref_i,
-      ppsg_cr_cnt_rst_o       => ppsg_cr_cnt_rst,
+      ppsg_cr_cnt_rst_o      => ppsg_cr_cnt_rst,
-      ppsg_cr_cnt_en_o        => ppsg_cr_cnt_en,
+      ppsg_cr_cnt_en_o       => ppsg_cr_cnt_en,
-      ppsg_cr_cnt_adj_o       => ppsg_cr_cnt_adj_o,
+      ppsg_cr_cnt_adj_o      => ppsg_cr_cnt_adj_o,
-      ppsg_cr_cnt_adj_i       => ppsg_cr_cnt_adj_i,
+      ppsg_cr_cnt_adj_i      => ppsg_cr_cnt_adj_i,
-      ppsg_cr_cnt_adj_load_o  => ppsg_cr_cnt_adj_load,
+      ppsg_cr_cnt_adj_load_o => ppsg_cr_cnt_adj_load,
-      ppsg_escr_sync_o      => ppsg_escr_sync_out,
+      ppsg_escr_sync_o       => ppsg_escr_sync_out,
-      ppsg_escr_sync_i      => ppsg_escr_sync_in,
+      ppsg_escr_sync_i       => ppsg_escr_sync_in,
-      ppsg_escr_sync_load_o => ppsg_escr_sync_load,
+      ppsg_escr_sync_load_o  => ppsg_escr_sync_load,
-      ppsg_cr_cnt_set_o       => ppsg_cr_cnt_set_p,
+      ppsg_cr_cnt_set_o      => ppsg_cr_cnt_set_p,
-      ppsg_cr_pwidth_o        => ppsg_cr_pwidth,
+      ppsg_cr_pwidth_o       => ppsg_cr_pwidth,
-      ppsg_cntr_nsec_i        => ppsg_cntr_nsec,
+      ppsg_cntr_nsec_i       => ppsg_cntr_nsec,
-      ppsg_cntr_utclo_i       => ppsg_cntr_utclo,
+      ppsg_cntr_utclo_i      => ppsg_cntr_utclo,
-      ppsg_cntr_utchi_i       => ppsg_cntr_utchi,
+      ppsg_cntr_utchi_i      => ppsg_cntr_utchi,
-      ppsg_adj_nsec_o         => ppsg_adj_nsec,
+      ppsg_adj_nsec_o        => ppsg_adj_nsec,
-      ppsg_adj_nsec_wr_o      => ppsg_adj_nsec_wr,
+      ppsg_adj_nsec_wr_o     => ppsg_adj_nsec_wr,
-      ppsg_adj_utclo_o        => ppsg_adj_utclo,
+      ppsg_adj_utclo_o       => ppsg_adj_utclo,
-      ppsg_adj_utclo_wr_o     => ppsg_adj_utclo_wr,
+      ppsg_adj_utclo_wr_o    => ppsg_adj_utclo_wr,
-      ppsg_adj_utchi_o        => ppsg_adj_utchi,
+      ppsg_adj_utchi_o       => ppsg_adj_utchi,
-      ppsg_adj_utchi_wr_o     => ppsg_adj_utchi_wr,
+      ppsg_adj_utchi_wr_o    => ppsg_adj_utchi_wr,
-      ppsg_escr_pps_val_o     => ppsg_escr_pps_val,
+      ppsg_escr_pps_valid_o  => ppsg_escr_pps_valid,
-      ppsg_escr_tc_val_o      => ppsg_escr_tc_val);
+      ppsg_escr_tm_valid_o   => ppsg_escr_tm_valid);
  -- start the adjustment upon write of 1 to CNT_ADJ bit
  cntr_adjust_p <= ppsg_cr_cnt_adj_load and ppsg_cr_cnt_adj_o;
@@ -404,18 +404,18 @@ begin  -- behavioral
  begin
    if rising_edge(clk_ref_i) then
      if(rst_synced_refclk = '0') then
-        ext_sync_p       <= '0';
+        ext_sync_p        <= '0';
-        sync_in_progress <= '0';
+        sync_in_progress  <= '0';
        ppsg_escr_sync_in <= '0';
      else
        if(ppsg_escr_sync_load = '1' and ppsg_escr_sync_out = '1') then
-          sync_in_progress     <= '1';
+          sync_in_progress  <= '1';
          ppsg_escr_sync_in <= '0';
        end if;
        if(sync_in_progress = '1' and pps_in_p = '1') then
-          ext_sync_p           <= '1';
+          ext_sync_p        <= '1';
-          sync_in_progress     <= '0';
+          sync_in_progress  <= '0';
          ppsg_escr_sync_in <= '1';
        else
          ext_sync_p <= '0';
@@ -424,9 +424,9 @@ begin  -- behavioral
    end if;
  end process;
-  tc_utc_o  <= std_logic_vector(cntr_utc);
+  tm_utc_o        <= std_logic_vector(cntr_utc);
-  tc_nsec_o <= std_logic_vector(cntr_nsec);
+  tm_cycles_o     <= std_logic_vector(cntr_nsec);
-  tc_val_o  <= ppsg_escr_tc_val;
+  tm_time_valid_o <= ppsg_escr_tm_valid;
-  pps_val_o <= ppsg_escr_pps_val;
+  pps_valid_o     <= ppsg_escr_pps_valid;
 end behavioral;
--- a/modules/wrsw_pps_gen/wrsw_pps_gen.wb
+++ b/modules/wrsw_pps_gen/wrsw_pps_gen.wb
@@ -174,7 +174,7 @@ peripheral {
         name = "PPS output valid";
         description = "write 1: PPS output provides reliable 1-PPS signal\
                        write 0: PPS output is invalid";
-         prefix = "PPS_VAL";
+         prefix = "PPS_VALID";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
@@ -182,10 +182,10 @@ peripheral {
      };
      field {
-         name = "Timecode output(UTC+nanosec) valid";
+         name = "Timecode output(UTC+cycles) valid";
         description = "write 1: Timecode output provides valid time\
                        write 0: Timecode output does not provide valid time";
-         prefix = "TC_VAL";
+         prefix = "TM_VALID";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;

--- a/modules/wrsw_pps_gen/xwb_pps_gen.vhd
+++ b/modules/wrsw_pps_gen/xwb_pps_gen.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-09-02
-- Last update: 2011-10-26
+-- Last update: 2011-10-27
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -38,10 +38,10 @@ entity xwb_pps_gen is
    clk_ref_i : in std_logic;
    clk_sys_i : in std_logic;
-    rst_n_i   : in std_logic;
+    rst_n_i : in std_logic;
-    slave_i   : in  t_wishbone_slave_in;
+    slave_i : in  t_wishbone_slave_in;
-    slave_o   : out t_wishbone_slave_out;
+    slave_o : out t_wishbone_slave_out;
    pps_in_i : in std_logic;
@@ -49,10 +49,10 @@ entity xwb_pps_gen is
    pps_csync_o : out std_logic;
    pps_out_o   : out std_logic;
-    pps_val_o   : out std_logic;
+    pps_valid_o     : out std_logic;
-    tc_utc_o    : out std_logic_vector(39 downto 0);
+    tm_utc_o        : out std_logic_vector(39 downto 0);
-    tc_nsec_o   : out std_logic_vector(27 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
-    tc_val_o    : out std_logic
+    tm_time_valid_o : out std_logic
  );
 end xwb_pps_gen;
@@ -65,56 +65,56 @@ architecture behavioral of xwb_pps_gen is
      g_address_granularity : t_wishbone_address_granularity
    );
    port (
-      clk_ref_i : in std_logic;
+      clk_ref_i       : in  std_logic;
-      clk_sys_i : in std_logic;
+      clk_sys_i       : in  std_logic;
-      rst_n_i   : in std_logic;
+      rst_n_i         : in  std_logic;
-      wb_addr_i : in  std_logic_vector(3 downto 0);
+      wb_addr_i       : in  std_logic_vector(3 downto 0);
-      wb_data_i : in  std_logic_vector(31 downto 0);
+      wb_data_i       : in  std_logic_vector(31 downto 0);
-      wb_data_o : out std_logic_vector(31 downto 0);
+      wb_data_o       : out std_logic_vector(31 downto 0);
-      wb_cyc_i  : in  std_logic;
+      wb_cyc_i        : in  std_logic;
-      wb_sel_i  : in  std_logic_vector(3 downto 0);
+      wb_sel_i        : in  std_logic_vector(3 downto 0);
-      wb_stb_i  : in  std_logic;
+      wb_stb_i        : in  std_logic;
-      wb_we_i   : in  std_logic;
+      wb_we_i         : in  std_logic;
-      wb_ack_o  : out std_logic;
+      wb_ack_o        : out std_logic;
-      wb_stall_o : out std_logic;
+      wb_stall_o      : out std_logic;
-      pps_in_i : in std_logic;
+      pps_in_i        : in  std_logic;
-      pps_csync_o : out std_logic;
+      pps_csync_o     : out std_logic;
-      pps_out_o   : out std_logic;
+      pps_out_o       : out std_logic;
-      pps_val_o   : out std_logic;
+      pps_valid_o     : out std_logic;
-      tc_utc_o    : out std_logic_vector(39 downto 0);
+      tm_utc_o        : out std_logic_vector(39 downto 0);
-      tc_nsec_o   : out std_logic_vector(27 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
-      tc_val_o    : out std_logic
+      tm_time_valid_o : out std_logic
    );
  end component;
 begin  -- behavioral
-  WRAPPED_PPSGEN: wrsw_pps_gen 
+  WRAPPED_PPSGEN : wrsw_pps_gen
    generic map(
      g_interface_mode      => g_interface_mode,
      g_address_granularity => g_address_granularity
    )
    port map(
-      clk_ref_i => clk_ref_i,
+      clk_ref_i       => clk_ref_i,
-      clk_sys_i => clk_sys_i,
+      clk_sys_i       => clk_sys_i,
-      rst_n_i   => rst_n_i,
+      rst_n_i         => rst_n_i,
-      wb_addr_i => slave_i.adr(3 downto 0),
+      wb_addr_i       => slave_i.adr(3 downto 0),
-      wb_data_i => slave_i.dat,
+      wb_data_i       => slave_i.dat,
-      wb_data_o => slave_o.dat,
+      wb_data_o       => slave_o.dat,
-      wb_cyc_i  => slave_i.cyc,
+      wb_cyc_i        => slave_i.cyc,
-      wb_sel_i  => slave_i.sel,
+      wb_sel_i        => slave_i.sel,
-      wb_stb_i  => slave_i.stb,
+      wb_stb_i        => slave_i.stb,
-      wb_we_i   => slave_i.we,
+      wb_we_i         => slave_i.we,
-      wb_ack_o  => slave_o.ack,
+      wb_ack_o        => slave_o.ack,
-      wb_stall_o => slave_o.stall,
+      wb_stall_o      => slave_o.stall,
-      pps_in_i    => pps_in_i,
+      pps_in_i        => pps_in_i,
-      pps_csync_o => pps_csync_o,
+      pps_csync_o     => pps_csync_o,
-      pps_out_o   => pps_out_o,
+      pps_out_o       => pps_out_o,
-      pps_val_o   => pps_val_o,
+      pps_valid_o     => pps_valid_o,
-      tc_utc_o    => tc_utc_o,
+      tm_utc_o        => tm_utc_o,
-      tc_nsec_o   => tc_nsec_o,
+      tm_cycles_o     => tm_cycles_o,
-      tc_val_o    => tc_val_o
+      tm_time_valid_o => tm_time_valid_o
    );
 end behavioral;