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White Rabbit core collection
Commit 44181219 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tristan Gingold
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wrc_core: use async assert, sync deassert reset

parent d0cc35be
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Showing with 17 additions and 17 deletions
modules/wrc_core/wrc_periph.vhd
View file @ 44181219
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-04-04
-- Last update: 2022-01-25
-- Last update: 2023-04-26
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -141,27 +141,28 @@ architecture struct of wrc_periph is
signal diag_out_regs : t_generic_word_array(g_diag_rw_size - 1 downto 0);
signal diag_in : t_generic_word_array(g_diag_ro_size + g_diag_rw_size-1 downto 0);
signal rst_net_n, rst_net_n_d0 : std_logic;
signal rst_wrc_n, rst_wrc_n_d0 : std_logic;
constant c_RESET_CHAIN_LENGTH : integer := 3;
signal rst_net_n, rst_wrc_n : std_logic;
signal rst_net_n_chain, rst_wrc_n_chain : std_logic_vector(c_RESET_CHAIN_LENGTH -1 downto 0);
begin
-- async assert, sync de-assert reset.
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
rst_wrc_n_o <= '0';
else
rst_net_n_o <= rst_net_n_d0;
rst_net_n_d0 <= rst_net_n;
rst_wrc_n_o <= rst_wrc_n_d0;
rst_wrc_n_d0 <= rst_wrc_n;
end if;
if rst_n_i = '0' then
rst_net_n_chain <= (others => '0');
rst_wrc_n_chain <= (others => '0');
elsif rising_edge(clk_sys_i) then
rst_net_n_chain <= rst_net_n & rst_net_n_chain(c_RESET_CHAIN_LENGTH-1 downto 1);
rst_wrc_n_chain <= rst_wrc_n & rst_wrc_n_chain(c_RESET_CHAIN_LENGTH-1 downto 1);
end if;
end process;
rst_wrc_n_o <= rst_wrc_n_chain(0);
rst_net_n_o <= rst_net_n_chain(0);
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -170,10 +171,9 @@ begin
if g_has_preinitialized_firmware then
rst_wrc_n <= '1';
else
rst_wrc_n <= '0'; -- no firmware in DPRAM? keep in reset so
-- that the CPU doesn't walk through the
-- whole address space trying to fetch
-- instructions (and sometimes freezing the interconnect)
-- no firmware in DPRAM? keep in reset so that the CPU doesn't walk through the
-- whole address space trying to fetch instructions (and sometimes freezing the interconnect)
rst_wrc_n <= '0';
end if;
else
......
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