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White Rabbit core collection
Commit 44f102fa authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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tricks and constraints so that the deltaTx/Rx calibration is not necessary for… 

tricks and constraints so that the deltaTx/Rx calibration is not necessary for every synthesized WRPC bitstream
parent 44ca0443
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Showing with 351 additions and 318 deletions
modules/wr_pps_gen/wr_pps_gen.vhd
View file @ 44f102fa
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2012-07-13
-- Last update: 2012-08-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -145,8 +145,9 @@ architecture behavioral of wr_pps_gen is
signal cntr_utc : unsigned (39 downto 0);
signal cntr_pps_ext : unsigned (24 downto 0);
signal ns_overflow : std_logic;
signal cntr_adjust_p : std_logic;
signal ns_overflow : std_logic;
signal ns_overflow_adv : std_logic;
signal cntr_adjust_p : std_logic;
signal adj_nsec : unsigned(27 downto 0);
signal adj_utc : unsigned(39 downto 0);
......@@ -172,7 +173,9 @@ architecture behavioral of wr_pps_gen is
signal pps_in_d0, pps_ext_d0, pps_ext_retimed : std_logic;
signal retime_counter : unsigned(4 downto 0);
signal pps_valid_int : std_logic;
signal pps_valid_int : std_logic;
signal pps_out_int : std_logic;
component chipscope_icon
......@@ -365,6 +368,7 @@ begin -- behavioral
if rst_synced_refclk = '0' or ppsg_cr_cnt_rst = '1' then
cntr_nsec <= (others => '0');
ns_overflow <= '0';
ns_overflow_adv <= '0';
adjust_in_progress_nsec <= '0';
adjust_done_nsec <= '1';
......@@ -381,16 +385,23 @@ begin -- behavioral
-- got SET TIME command - load the counter with new value
if(ppsg_cr_cnt_set_p = '1' or ext_sync_p = '1') then
cntr_nsec <= adj_nsec;
cntr_nsec <= adj_nsec;
adjust_done_nsec <= '1';
ns_overflow <= '0';
ns_overflow <= '0';
ns_overflow_adv <= '0';
-- got counter overflow:
elsif(cntr_nsec = to_unsigned(c_PERIOD-3, cntr_nsec'length)) then
ns_overflow <= '0';
ns_overflow_adv <= '1';
cntr_nsec <= cntr_nsec + 1;
elsif(cntr_nsec = to_unsigned(c_PERIOD-2, cntr_nsec'length)) then
ns_overflow <= '1';
cntr_nsec <= cntr_nsec + 1;
ns_overflow <= '1';
ns_overflow_adv <= '0';
cntr_nsec <= cntr_nsec + 1;
elsif(cntr_nsec = to_unsigned(c_PERIOD-1, cntr_nsec'length)) then
ns_overflow <= '0';
ns_overflow <= '0';
ns_overflow_adv <= '0';
-- we're in the middle of offset adjustment - load the counter with
-- offset value instead of resetting it. This equals to subtracting the offset
-- but takes less logic.
......@@ -403,8 +414,9 @@ begin -- behavioral
cntr_nsec <= (others => '0');
end if;
else
ns_overflow <= '0';
cntr_nsec <= cntr_nsec + 1;
ns_overflow <= '0';
ns_overflow_adv <= '0';
cntr_nsec <= cntr_nsec + 1;
end if;
end if;
end if;
......@@ -415,11 +427,11 @@ begin -- behavioral
begin
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' then
pps_valid_int <= '1';
pps_valid_int <= '1';
ns_overflow_2nd <= '0';
else
if(sync_in_progress = '1' or adjust_in_progress_nsec = '1' or adjust_in_progress_utc = '1') then
pps_valid_int <= '0';
pps_valid_int <= '0';
ns_overflow_2nd <= '0';
elsif(adjust_in_progress_utc = '0' and adjust_in_progress_nsec = '0' and sync_in_progress = '0') then
......@@ -473,16 +485,16 @@ begin -- behavioral
begin
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' then
pps_out_o <= '0';
width_cntr <= (others => '0');
pps_out_int <= '0';
width_cntr <= (others => '0');
else
if(ns_overflow = '1') then
pps_out_o <= ppsg_escr_pps_valid;
width_cntr <= unsigned(ppsg_cr_pwidth);
if(ns_overflow_adv = '1') then
pps_out_int <= ppsg_escr_pps_valid;
width_cntr <= unsigned(ppsg_cr_pwidth);
else
if(width_cntr = to_unsigned(0, width_cntr'length)) then
pps_out_o <= '0';
pps_out_int <= '0';
else
width_cntr <= width_cntr -1;
end if;
......@@ -492,6 +504,16 @@ begin -- behavioral
end process;
process(clk_ref_i, rst_synced_refclk)
begin
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' then
pps_out_o <= '0';
else
pps_out_o <= pps_out_int;
end if;
end if;
end process;
-- pps_out_o <=pps_ext_retimed;
......@@ -537,7 +559,7 @@ begin -- behavioral
ppsg_cr_cnt_adj_i <= pps_valid_int;
pps_valid_o <= pps_valid_int;
tm_utc_o <= std_logic_vector(cntr_utc);
tm_cycles_o <= std_logic_vector(cntr_nsec);
tm_time_valid_o <= ppsg_escr_tm_valid;
......
syn/spec_1_1/wr_core_demo/spec_top_wrc.xise
View file @ 44f102fa
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top/spec_1_1/wr_core_demo/spec_top.ucf
View file @ 44f102fa
......@@ -43,7 +43,6 @@ NET "thermo_id" IOSTANDARD = "LVCMOS25";
#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "PRSNT_M2C_L" LOC = A2;
#NET "PRSNT_M2C_L" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF1_b" LOC = C17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
......@@ -267,8 +266,6 @@ NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
#NET "LA07_N" IOSTANDARD = "LVCMOS25";
#NET "LA07_P" LOC = U9;
#NET "LA07_P" IOSTANDARD = "LVCMOS25";
#NET "LA08_N" LOC = R8;
#NET "LA08_N" IOSTANDARD = "LVCMOS25";
#NET "LA08_P" LOC = R9;
......@@ -503,7 +500,6 @@ TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_i
## Pin definitions for FmcDio5chttl + SPEC v1.1/2.0 ##
########################################################
# DIO outputs
NET "dio_p_o[4]" LOC= T8;
NET "dio_n_o[4]" LOC= U8;
NET "dio_p_o[4]" IOSTANDARD=LVDS_25;
......@@ -537,7 +533,6 @@ NET "dio_sdn_ck_n_o" LOC= Y5;
NET "dio_sdn_ck_n_o" IOSTANDARD=LVCMOS25;
# DIO output enable/termination enable
NET "dio_oe_n_o[4]" LOC= AA6;
NET "dio_oe_n_o[3]" LOC= W10;
NET "dio_oe_n_o[2]" LOC= W11;
......@@ -566,7 +561,6 @@ NET "dio_onewire_b" LOC=AB16;
NET "dio_onewire_b" IOSTANDARD=LVCMOS25;
# DIO inputs
NET "dio_clk_p_i" LOC=L20;
NET "dio_clk_p_i" IOSTANDARD=LVDS_25;
......@@ -641,3 +635,11 @@ TIMESPEC TS_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "U_GTP/ch0_gtp_clkout_int<1>" 8
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" TNM = skew_limit;
INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].DMTD_FB/clk_in" TNM = skew_limit;
INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/08
INST "U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o" TNM = rx_ts_trig;
TIMESPEC TS_RXTS = FROM "rx_ts_trig" TO "FFS" 1 ns DATAPATHONLY;
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 44f102fa
......@@ -810,7 +810,7 @@ begin
port map (
clk_i => clk_125m_pllref,
rst_n_i => local_reset_n,
pulse_i => pps,
pulse_i => '0', --pps,
extended_o => dio_led_top_o);
......
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