arria5: negative edge according to final arria5 timing model

The final timing model is first available in quartus 13.0sp1

arria5: negative edge according to final arria5 timing model
The final timing model is first available in quartus 13.0sp1
45e67ea3 · Wesley W. Terpstra · fbd496c1 · 45e67ea3 · 45e67ea3
Commit 45e67ea3 authored Aug 14, 2013 by Wesley W. Terpstra
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Showing with 2 additions and 2 deletions

altera_pkg.vhd platform/altera/altera_pkg.vhd +1 -1

wr_arria5_phy.vhd platform/altera/wr_arria5_phy/wr_arria5_phy.vhd +1 -1

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--- a/platform/altera/altera_pkg.vhd
+++ b/platform/altera/altera_pkg.vhd
@@ -61,7 +61,7 @@ package wr_altera_pkg is
  component wr_arria5_phy is
    generic (
      g_tx_latch_edge : std_logic := '1';
-      g_rx_latch_edge : std_logic := '1');
+      g_rx_latch_edge : std_logic := '0');
    port (
      clk_reconf_i   : in  std_logic;
      clk_pll_i      : in  std_logic;

--- a/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
+++ b/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
@@ -50,7 +50,7 @@ use work.disparity_gen_pkg.all;
 entity wr_arria5_phy is
  generic (
    g_tx_latch_edge : std_logic := '1';
-    g_rx_latch_edge : std_logic := '1');
+    g_rx_latch_edge : std_logic := '0');
  port (
    clk_reconf_i : in  std_logic; -- 50 MHz
    clk_pll_i    : in  std_logic; -- feeds transmitter PLL