top/vfchd: Introduce VFC-HD reference design

479c1ff2 · Dimitris Lampridis · 7eaac3d8 · 479c1ff2 · 479c1ff2 · 479c1ff2
Commit 479c1ff2 authored Feb 01, 2017 by Dimitris Lampridis
10 changed files
--- a/syn/vfchd_ref_design/Manifest.py
+++ b/syn/vfchd_ref_design/Manifest.py
+target = "altera"
+action = "synthesis"
+
+syn_family  = "Arria V"
+syn_device  = "5agxmb1g4f"
+syn_grade   = "c4"
+syn_package = "40"
+
+syn_top     = "vfchd_wr_ref_top"
+syn_project = "vfchd_wr_ref"
+
+syn_tool = "quartus"
+
+quartus_preflow = "quartus_preflow.tcl"
+
+files = [
+    "vfchd_wr_ref.sdc",
+    "quartus_preflow.tcl",
+]
+
+modules = {
+    "local" : [
+        "../../top/vfchd_ref_design/",
+    ]
+}
--- a/syn/vfchd_ref_design/quartus_preflow.tcl
+++ b/syn/vfchd_ref_design/quartus_preflow.tcl
+# Quartus II: Tcl Preflow File for VFC-HD WR PTP core reference design
+
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+# Borrowed and adjusted from GSI bel-projects
+proc qmegawiz {files} {
+  set dir [file dirname [info script]]
+  post_message "Testing for megawizard regeneration in $dir:$files"
+
+  set device  [ get_global_assignment -name DEVICE ]
+  set family  [ get_global_assignment -name FAMILY ]
+
+  foreach i $files {
+    if {![file exists "$dir/$i.qip"] || [file mtime "$dir/$i.txt"] > [file mtime "$dir/$i.qip"]} {
+      post_message -type info "Regenerating $i using qmegawiz"
+      file delete "$dir/$i.qip"
+      file copy -force "$dir/$i.txt" "$dir/$i.vhd"
+
+      set sf [open "| qmegawiz -silent \"-defaultfamily:$family\" \"-defaultdevice:$device\" \"$dir/$i.vhd\" " "r"]
+      while {[gets $sf line] >= 0} { post_message -type info "$line" }
+      if {[catch {close $sf} err]} {
+	post_message -type error "Executing qmegawiz: $err"
+	exit 1
+      }
+      if {![file exists "$dir/$i.qip"]} {
+	post_message -type error "Executing qmegawiz: did not create $dir/$i.qip!"
+	exit 1
+      }
+
+      file mtime "$dir/$i.qip" [file mtime "$dir/$i.vhd"]
+    }
+      set_global_assignment -name QIP_FILE "$dir/$i.qip"
+  }
+}
+
+# procedure to delete an existing global assignment
+proc del_global_assignment {name value} {
+    set_global_assignment -name $name -remove $value
+}
+
+# procedure to check if signal is input
+proc is_input {signal} {
+    return [regexp -nocase {.+_i(\[[0123456789]+\])?$} $signal]
+}
+
+# simple procedure to take care of location assignments
+proc loc {pin signal {iostandard "default"} {pullup "off"}} {
+    set_location_assignment "PIN_${pin}" -to $signal
+    if {![string equal $iostandard "default"]} {
+	set_instance_assignment -name IO_STANDARD $iostandard -to $signal
+    } else {
+	set_instance_assignment -name IO_STANDARD "2.5 V" -to $signal
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to $signal
+	if {![is_input $signal]} {
+	    set_instance_assignment -name SLEW_RATE 1 -to $signal
+	}
+    }
+    if {![string equal $pullup "off"]} {
+	set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to $signal
+    }
+}
+
+# SCRIPT EXECUTION STARTS HERE
+post_message "Executing WR VFC-HD reference design pre-flow script"
+
+set project_name "vfchd_wr_ref"
+
+set make_assignments 0
+
+# Make sure that the right project is open
+if {[is_project_open]} {
+    if {[string compare $quartus(project) $project_name]} {
+	project_close
+	project_open $project_name
+    }
+} else {
+    project_open $project_name
+}
+
+# Remove unused megafunctions to reduce number of warnings
+del_global_assignment QIP_FILE "../../ip_cores/general-cores/platform/altera/networks/arria5_networks.qip"
+del_global_assignment QIP_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/arria5_pcie.qip"
+
+# Regenerate required megafunctions if necessary
+source ../../platform/altera/wr_arria5_phy/wr_arria5_phy.tcl
+source ../../platform/altera/wr_arria5_pll_default/wr_arria5_pll_default.tcl
+
+# Global assignments
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS"
+
+# I/O configuration
+loc AW25 areset_n_i
+loc AF8  clk_board_125m_i "LVDS"
+loc AD20 clk_board_20m_i
+
+loc AF25 dac_dmtd_sync_n_o
+loc AC24 dac_ref_sync_n_o
+loc AH26 dac_sclk_o
+loc AG26 dac_din_o
+
+loc AE1  sfp_rx_i "1.5-V PCML"
+loc AD3  sfp_tx_o "1.5-V PCML"
+
+loc AN25 i2c_mux_sda_b
+loc AM25 i2c_mux_scl_b
+
+loc AT26 io_exp_irq_bsteth_n_i "default" "on"
+loc AK25 io_exp_irq_los_n_i    "default" "on"
+
+loc AD26 eeprom_sda_b
+loc AH25 eeprom_scl_b
+
+loc AV27 onewire_b
+
+loc AW28 vme_write_n_i
+loc AW30 vme_lword_n_b
+loc AK21 vme_iackout_n_o
+loc AM21 vme_iackin_n_i
+loc AN21 vme_iack_n_i
+loc AL22 vme_dtack_oe_o
+loc AP22 vme_ds_n_i[0]
+loc AN22 vme_ds_n_i[1]
+loc AW20 vme_data_oe_n_o
+loc AW19 vme_data_dir_o
+loc AE29 vme_as_n_i
+loc AK27 vme_addr_oe_n_o
+loc AJ27 vme_addr_dir_o
+loc AK22 vme_irq_n_o[1]
+loc AT21 vme_irq_n_o[2]
+loc AR21 vme_irq_n_o[3]
+loc AH22 vme_irq_n_o[4]
+loc AG22 vme_irq_n_o[5]
+loc AU20 vme_irq_n_o[6]
+loc AT20 vme_irq_n_o[7]
+loc AD24 vme_data_b[0]
+loc AD23 vme_data_b[1]
+loc AU24 vme_data_b[2]
+loc AT24 vme_data_b[3]
+loc AL24 vme_data_b[4]
+loc AK24 vme_data_b[5]
+loc AF24 vme_data_b[6]
+loc AE24 vme_data_b[7]
+loc AH24 vme_data_b[8]
+loc AG24 vme_data_b[9]
+loc AW24 vme_data_b[10]
+loc AW23 vme_data_b[11]
+loc AP24 vme_data_b[12]
+loc AN24 vme_data_b[13]
+loc AU23 vme_data_b[14]
+loc AT23 vme_data_b[15]
+loc AP23 vme_data_b[16]
+loc AN23 vme_data_b[17]
+loc AE23 vme_data_b[18]
+loc AD22 vme_data_b[19]
+loc AL23 vme_data_b[20]
+loc AK23 vme_data_b[21]
+loc AU22 vme_data_b[22]
+loc AT22 vme_data_b[23]
+loc AW22 vme_data_b[24]
+loc AV22 vme_data_b[25]
+loc AW21 vme_data_b[26]
+loc AV21 vme_data_b[27]
+loc AH23 vme_data_b[28]
+loc AG23 vme_data_b[29]
+loc AF22 vme_data_b[30]
+loc AE22 vme_data_b[31]
+loc AD29 vme_am_i[0]
+loc AH30 vme_am_i[1]
+loc AG30 vme_am_i[2]
+loc AV31 vme_am_i[3]
+loc AU31 vme_am_i[4]
+loc AW31 vme_am_i[5]
+loc AL30 vme_addr_b[1]
+loc AK30 vme_addr_b[2]
+loc AT30 vme_addr_b[3]
+loc AR30 vme_addr_b[4]
+loc AV30 vme_addr_b[5]
+loc AU30 vme_addr_b[6]
+loc AU29 vme_addr_b[7]
+loc AT29 vme_addr_b[8]
+loc AP30 vme_addr_b[9]
+loc AN30 vme_addr_b[10]
+loc AP29 vme_addr_b[11]
+loc AN29 vme_addr_b[12]
+loc AC29 vme_addr_b[13]
+loc AB29 vme_addr_b[14]
+loc AG28 vme_addr_b[15]
+loc AF28 vme_addr_b[16]
+loc AL29 vme_addr_b[17]
+loc AK29 vme_addr_b[18]
+loc AJ28 vme_addr_b[19]
+loc AH28 vme_addr_b[20]
+loc AE28 vme_addr_b[21]
+loc AD28 vme_addr_b[22]
+loc AB28 vme_addr_b[23]
+loc AB27 vme_addr_b[24]
+loc AM28 vme_addr_b[25]
+loc AD27 vme_addr_b[26]
+loc AC27 vme_addr_b[27]
+loc AR28 vme_addr_b[28]
+loc AP28 vme_addr_b[29]
+loc AV28 vme_addr_b[30]
+loc AU28 vme_addr_b[31]
+
+loc AM27 fmc_enable_n_o
+loc C20  dio_led_term_o
+loc D20  dio_led_out_o
+loc M27  dio1_i "LVDS"
+loc AK34 dio5_clk_i
+loc R26  dio1_oe_n_o
+loc C28  dio5_oe_n_o
+loc T27  dio1_term_en_o
+loc C27  dio5_term_en_o
+
+loc AL26 vfchd_gpio3_o
+loc AV24 vfchd_gpio4_o
+
+# Commit assignments
+export_assignments
+
+# SCRIPT EXECUTION ENDS HERE
+post_message "WR VFC-HD reference design pre-flow script execution complete"
--- a/syn/vfchd_ref_design/vfchd_wr_ref.sdc
+++ b/syn/vfchd_ref_design/vfchd_wr_ref.sdc
+# Clock inputs
+create_clock -name clk_10m_ext -period 100.0 [get_ports dio5_clk_i]
+create_clock -name clk_125m    -period   8.0 [get_ports clk_board_125m_i]
+create_clock -name clk_20m     -period  50.0 [get_ports clk_board_20m_i]
+
+# Derive the PLL Output clocks automatically
+derive_pll_clocks
+derive_clock_uncertainty
+
+# splitting of PHY clocks based on pexarria5 project from GSI
+set_clock_groups -asynchronous                                                       \
+    -group { clk_10m_ext                                                             \
+             cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_ext_ref_pll|* }             \
+    -group { clk_125m                                                                \
+             cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_sys_clk_pll|*|general[0]*   \
+             cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_sys_clk_pll|*|general[1]* } \
+    -group { clk_20m                                                                 \
+             cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_dmtd_clk_pll|* }            \
+    -group { cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*.cdr_refclk*           \
+             cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*.cmu_pll.*             \
+             cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|av_tx_pma|*           \
+             cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|inst_av_pcs|*|tx* }   \
+    -group { cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|clk90bdes             \
+             cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|clk90b                \
+             cmp_xwrc_board_vfchd|cmp_xwrc_platform|*cmp_phy|*|rcvdclkpma }
+
+# False paths from/to all otherwise unconstrained I/O
+set_false_path -from [get_ports *]
+set_false_path -to [get_ports *]
--- a/top/vfchd_ref_design/Manifest.py
+++ b/top/vfchd_ref_design/Manifest.py
+fetchto = "../../ip_cores"
+
+files = [
+    "vfchd_wr_ref_top.vhd",
+    "vfchd_i2cmux/vfchd_i2cmux_pkg.vhd",
+    "vfchd_i2cmux/I2cMuxAndExpReqArbiter.v",
+    "vfchd_i2cmux/I2cMuxAndExpMaster.v",
+    "vfchd_i2cmux/SfpIdReader.v",
+]
+
+modules = {
+    "local" : [
+        "../../",
+        "../../board/vfchd",
+    ],
+    "git" : [
+        "git://ohwr.org/hdl-core-lib/general-cores.git",
+        "git://ohwr.org/hdl-core-lib/vme64x-core.git",
+        "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+    ],
+}
--- a/top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpMaster.v
+++ b/top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpMaster.v
+//============================================================================================\\
+//##################################   Module Information   ##################################\\
+//============================================================================================\\
+//                                                                                         
+// Company: CERN (BE-BI) 
+//                                                        
+// File Name: I2cExpAndMuxMaster.v  
+//
+// File versions history:
+//
+//       DATE          VERSION      AUTHOR             DESCRIPTION
+//     - <date>        <version>    Andrea Boccardi    <description>               
+//
+// Language: Verilog 2005                                                              
+//
+// Description:
+// 
+//      The requests are level sensitive and accepted when the module is not busy.
+//                                                                                                   
+//============================================================================================\\
+//############################################################################################\\
+//============================================================================================\\
+
+`timescale 1ns/100ps 
+
+module I2cExpAndMuxMaster 
+//====================================  Global Parameters  ===================================\\   
+#(  parameter g_SclHalfPeriod = 10'd256)      
+//========================================  I/O ports  =======================================\\    
+
+(   
+    //==== Clocks & Resets ====\\ 
+    input             Clk_ik,
+    input             Rst_irq,
+    //==== Access requests ====\\
+    // IO Expanders parameters:
+    input             IoExpWrReq_i,    
+    output reg        IoExpWrOn_oq,
+    input             IoExpRdReq_i,     
+    output reg        IoExpRdOn_oq,    
+    input       [2:0] IoExpAddr_ib3,
+    input       [1:0] IoExpRegAddr_ib2, 
+    input       [7:0] IoExpData_ib8,  
+    // I2C Mux parameters:
+    input             I2cSlaveWrReq_i,
+    output reg        I2cSlaveWrOn_o,
+    input             I2cSlaveRdReq_i,
+    output reg        I2cSlaveRdOn_o,    
+    input             I2cMuxAddress_i,
+    input       [1:0] I2cMuxChannel_ib2, 
+    input       [6:0] I2cSlaveAddr_ib7,
+    input       [7:0] I2cSlaveRegAddr_ib8,
+    input       [7:0] I2cSlaveByte_ib8,   
+    // Status and results: 
+    output reg        Busy_o,
+    output reg        NewByteRead_op,
+    output reg  [7:0] ByteOut_ob8,
+    output reg        AckError_op,    
+    //==== I2C Bus ====\\ 
+    inout             Scl_ioz,
+    inout             Sda_ioz    
+);     
+   
+//=======================================  Declarations  =====================================\\    
+//==== Local parameters ====\\ 
+// FSM:
+localparam  s_Idle              = 4'h0,
+            s_FetchCommand      = 4'h1,
+            s_StartExecution    = 4'h2,
+            s_StartSda1         = 4'h3,
+            s_StartScl1         = 4'h4,
+            s_StartSda0         = 4'h5,
+            s_StartScl0         = 4'h6,
+            s_SendScl0          = 4'h7,
+            s_SendScl1          = 4'h8,
+            s_GetScl0           = 4'h9,
+            s_GetScl1           = 4'ha,
+            s_StopSda0          = 4'hb,
+            s_StopScl1          = 4'hc,
+            s_StopSda1          = 4'hd;
+// Command sequence ROM:
+localparam  c_IoExpWriteSeq     = 3'd0,
+            c_IoExpReadSeq      = 3'd1,
+            c_I2cSlaveRead      = 3'd2,  
+            c_I2cSlaveWrite     = 3'd3;
+// Commands:
+localparam  c_SendStartBit  = 3'd1, 
+            c_SendStopBit   = 3'd2,
+            c_SendByte      = 3'd3,
+            c_GetByte       = 3'd4,
+            c_GoToIdle      = 3'b0;           
+
+//==== Wires & Regs ====\\ 
+// FSM
+reg [3:0] State_qb4, NextState_ab4;    
+// Support Logic
+reg [2:0] Command_b3;
+reg [9:0] SclCounter_c10; 
+reg [3:0] BitCounter_c4;
+reg       SclOe_e, SdaOe_e;        
+reg       I2CAck;  
+reg [7:0] ShReg_b8;   
+reg [2:0] ActiveSequence_b3;  
+// Command Sequences  
+reg  [3:0] CommandPointer_c4;          
+reg [10:0] IoExpWriteSeq_b11, IoExpReadSeq_b11;
+reg  [2:0] IoExpAddr_qb3;
+reg  [1:0] IoExpRegAddr_qb2;
+reg  [7:0] IoExpData_qb8; 
+reg [10:0] I2cMuxRdSlaveRegSeq_b11, I2cMuxWrSlaveRegSeq_b11;
+reg        I2cMuxAddress_q;
+reg  [1:0] I2cMuxChannel_qb2; 
+reg  [6:0] I2cSlaveAddr_qb7;
+reg  [7:0] I2cSlaveRegAddr_qb8;
+reg  [7:0] I2cSlaveByte_qb8;   
+
+//=======================================  User Logic  =======================================\\    
+
+//==== I2C command's sequences ====\\ 
+// Writing a value in a register of one IO expander  
+always @(posedge Clk_ik) case(CommandPointer_c4) 
+    4'd0: IoExpWriteSeq_b11    <= #1 {c_SendStartBit, 8'h0};
+    4'd1: IoExpWriteSeq_b11    <= #1 {c_SendByte, 4'b0100, IoExpAddr_qb3, 1'b0}; //Comment: Selection of the Slave in write mode
+    4'd2: IoExpWriteSeq_b11    <= #1 {c_SendByte, 6'b0, IoExpRegAddr_qb2};       //Comment: Writing the Register address
+    4'd3: IoExpWriteSeq_b11    <= #1 {c_SendByte, IoExpData_qb8};                //Comment: Writing the Register Value
+    4'd4: IoExpWriteSeq_b11    <= #1 {c_SendStopBit, 8'h0};
+    default: IoExpWriteSeq_b11 <= #1 {c_GoToIdle, 8'h0};
+endcase
+    
+// Reading a value from a register of one IO expander   
+always @(posedge Clk_ik) case(CommandPointer_c4) 
+    4'd0: IoExpReadSeq_b11    <= #1 {c_SendStartBit, 8'h0};
+    4'd1: IoExpReadSeq_b11    <= #1 {c_SendByte, 4'b0100, IoExpAddr_qb3, 1'b0}; //Comment: Selection of the Slave in write mode
+    4'd2: IoExpReadSeq_b11    <= #1 {c_SendByte, 6'b0, IoExpRegAddr_qb2};       //Comment: Writing the Register address
+    4'd3: IoExpReadSeq_b11    <= #1 {c_SendStartBit, 8'h0};                     //Comment: Repeated start (new cycle)
+    4'd4: IoExpReadSeq_b11    <= #1 {c_SendByte, 4'b0100, IoExpAddr_qb3, 1'b1}; //Comment: Selection of the Slave in read mode
+    4'd5: IoExpReadSeq_b11    <= #1 {c_GetByte, 8'h1};                           //Comment: Read of the last Byte (single read)
+    4'd6: IoExpReadSeq_b11    <= #1 {c_SendStopBit, 8'h0};
+    default: IoExpReadSeq_b11 <= #1 {c_GoToIdle, 8'h0};  
+endcase
+
+// Reading a register from a device attached to a I2C mux
+always @(posedge Clk_ik) case(CommandPointer_c4) 
+    4'h0: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendStartBit, 8'h0};
+    4'h1: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendByte, 6'h38, I2cMuxAddress_q, 1'b0};  //Comment: Selection of the I2C Mux in Write mode
+    4'h2: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendByte, 5'b0, 1'b1, I2cMuxChannel_qb2}; //Comment: Enabling the desired channel 
+    4'h3: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendStopBit, 8'h0};
+    4'h4: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendStartBit, 8'h0};
+    4'h5: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendByte, I2cSlaveAddr_qb7, 1'b0};         //Comment: Selection of the Slave in write mode
+    4'h6: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendByte, I2cSlaveRegAddr_qb8};            //Comment: Writing the Register address
+    4'h7: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendStartBit, 8'h0};                      //Comment: Repeated start (new cycle)
+    4'h8: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendByte, I2cSlaveAddr_qb7, 1'b1};         //Comment: Selection of the Slave in read mode
+    4'h9: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_GetByte, 8'h1};                           //Comment: Read of the last Byte (single read)
+    4'ha: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendStopBit, 8'h0};
+    4'hb: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendStartBit, 8'h0};
+    4'hc: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendByte, 6'h38, I2cMuxAddress_q, 1'b0}; //Comment: Selection of the I2C Mux  in Write mode
+    4'hd: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendByte, 5'b0, 3'b0};                   //Comment: Disabling all channels 
+    4'he: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_SendStopBit, 8'h0};        
+    default: I2cMuxRdSlaveRegSeq_b11 <= #1 {c_GoToIdle, 8'h0};
+endcase
+
+// Writing a register from a device attached to a I2C mux
+always @(posedge Clk_ik) case(CommandPointer_c4) 
+    4'h0: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendStartBit, 8'h0};
+    4'h1: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendByte, 6'h38, I2cMuxAddress_q, 1'b0};  //Comment: Selection of the I2C Mux in Write mode
+    4'h2: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendByte, 5'b0, 1'b1, I2cMuxChannel_qb2}; //Comment: Enabling the desired channel 
+    4'h3: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendStopBit, 8'h0};
+    4'h4: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendStartBit, 8'h0};
+    4'h5: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendByte, I2cSlaveAddr_qb7, 1'b0};         //Comment: Selection of the Slave in write mode
+    4'h6: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendByte, I2cSlaveRegAddr_qb8};            //Comment: Writing the Register address
+    4'h7: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendByte, I2cSlaveByte_qb8};               //Comment: Sending the byte
+    4'h8: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendStopBit, 8'h0};
+    4'h9: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendStartBit, 8'h0};
+    4'ha: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendByte, 6'h38, I2cMuxAddress_q, 1'b0}; //Comment: Selection of the I2C Mux  in Write mode
+    4'hb: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendByte, 5'b0, 3'b0};                   //Comment: Disabling all channels 
+    4'hc: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_SendStopBit, 8'h0};        
+    default: I2cMuxWrSlaveRegSeq_b11 <= #1 {c_GoToIdle, 8'h0};
+endcase
+ 
+//==== State Machine ====\\ 
+always @(posedge Clk_ik) State_qb4 <= #1 Rst_irq ?  s_Idle :  NextState_ab4;
+
+always @* begin
+    NextState_ab4 =  State_qb4;
+    case(State_qb4)
+    // Waiting for a request
+    s_Idle: if (~Busy_o&&(IoExpWrReq_i || IoExpRdReq_i || I2cSlaveWrReq_i || I2cSlaveRdReq_i)) NextState_ab4 = s_FetchCommand;
+    // Fetching and decoding the command
+    s_FetchCommand: NextState_ab4 =  s_StartExecution;
+    s_StartExecution: if (Command_b3 == c_SendStartBit) NextState_ab4 = s_StartSda1;
+                 else if (Command_b3 == c_SendByte)     NextState_ab4 = s_SendScl0;
+                 else if (Command_b3 == c_GetByte)      NextState_ab4 = s_GetScl0;
+                 else if (Command_b3 == c_SendStopBit)  NextState_ab4 = s_StopSda0;
+                 else if (Command_b3 == c_GoToIdle)     NextState_ab4 = s_Idle; 
+    // Start bit sequence            
+    s_StartSda1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StartScl1;
+    s_StartScl1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StartSda0;
+    s_StartSda0: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StartScl0;
+    s_StartScl0: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_FetchCommand;
+    // Byte sending sequence            
+    s_SendScl0: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = (BitCounter_c4==4'd9) ? s_FetchCommand : s_SendScl1;
+    s_SendScl1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_SendScl0;
+    // Byte getting sequence                          
+    s_GetScl0 : if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = (BitCounter_c4==4'd9) ? s_FetchCommand : s_GetScl1;
+    s_GetScl1 : if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_GetScl0;
+    // Stop bit sequence                      
+    s_StopSda0: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StopScl1;
+    s_StopScl1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StopSda1;
+    s_StopSda1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_FetchCommand;
+    // Protection from bad state condition            
+    default: NextState_ab4 = s_Idle;
+    endcase 
+end 
+  
+always @(posedge Clk_ik) begin
+    if  (Rst_irq) begin
+        BitCounter_c4       <= #1  4'b0;
+        SclCounter_c10      <= #1 10'b0;
+        I2CAck              <= #1  1'b0;  
+        ShReg_b8            <= #1  8'b0; 
+        Command_b3          <= #1  3'b0;      
+        CommandPointer_c4   <= #1  4'h0;
+        ActiveSequence_b3   <= #1  3'b0;
+        ByteOut_ob8         <= #1  8'b0;
+        SclOe_e             <= #1 1'b0;
+        SdaOe_e             <= #1 1'b0;   
+        Busy_o              <= #1 1'b0;
+        IoExpWrOn_oq        <= #1 1'b0;
+        IoExpRdOn_oq        <= #1 1'b0;
+        I2cSlaveWrOn_o      <= #1 1'b0;
+        I2cSlaveRdOn_o      <= #1 1'b0;   
+        NewByteRead_op      <= #1 1'b0;
+    end else case(State_qb4)
+        // Waiting for a request    
+        s_Idle : begin
+            SclOe_e             <= #1 1'b0;
+            SdaOe_e             <= #1 1'b0;         
+            CommandPointer_c4   <= #1 4'h0; 
+            IoExpWrOn_oq        <= #1 1'b0;
+            IoExpRdOn_oq        <= #1 1'b0;
+            I2cSlaveWrOn_o      <= #1 1'b0;
+            I2cSlaveRdOn_o      <= #1 1'b0; 
+            Busy_o              <= #1 1'b0;
+            NewByteRead_op      <= #1 1'b0;
+            if (NextState_ab4 != s_Idle) begin
+                AckError_op <= #1 1'b0;  
+                Busy_o      <= #1 1'b1;                
+                if (IoExpWrReq_i) begin    
+                    ActiveSequence_b3   <= #1 c_IoExpWriteSeq;
+                    IoExpWrOn_oq        <= #1 1'b1;
+                    IoExpAddr_qb3       <= #1 IoExpAddr_ib3;
+                    IoExpRegAddr_qb2    <= #1 IoExpRegAddr_ib2;
+                    IoExpData_qb8       <= #1 IoExpData_ib8;                        
+                end else if (IoExpRdReq_i) begin
+                    ActiveSequence_b3   <= #1 c_IoExpReadSeq;   
+                    IoExpRdOn_oq        <= #1 1'b1;
+                    IoExpAddr_qb3       <= #1 IoExpAddr_ib3;
+                    IoExpRegAddr_qb2    <= #1 IoExpRegAddr_ib2;
+                end else if (I2cSlaveWrReq_i) begin
+                    ActiveSequence_b3   <= #1 c_I2cSlaveWrite;   
+                    I2cSlaveWrOn_o      <= #1 1'b1; 
+                    I2cMuxAddress_q     <= #1 I2cMuxAddress_i;
+                    I2cMuxChannel_qb2   <= #1 I2cMuxChannel_ib2;
+                    I2cSlaveAddr_qb7    <= #1 I2cSlaveAddr_ib7;    
+                    I2cSlaveRegAddr_qb8 <= #1 I2cSlaveRegAddr_ib8;  
+                    I2cSlaveByte_qb8    <= #1 I2cSlaveByte_ib8;                         
+                end else if (I2cSlaveRdReq_i) begin
+                    ActiveSequence_b3   <= #1 c_I2cSlaveRead;   
+                    I2cSlaveRdOn_o      <= #1 1'b1;
+                    I2cMuxAddress_q     <= #1 I2cMuxAddress_i;
+                    I2cMuxChannel_qb2   <= #1 I2cMuxChannel_ib2;
+                    I2cSlaveAddr_qb7    <= #1 I2cSlaveAddr_ib7;    
+                    I2cSlaveRegAddr_qb8 <= #1 I2cSlaveRegAddr_ib8;  
+                end 
+            end
+        end
+       // Fetching and decoding the command
+        s_FetchCommand: begin
+            NewByteRead_op    <= #1 Command_b3 == c_GetByte;
+            ByteOut_ob8       <= #1 ShReg_b8;   
+            AckError_op       <= #1 Command_b3 == c_SendByte &&  I2CAck;   
+            CommandPointer_c4 <= #1 CommandPointer_c4 + 1'b1;
+            case (ActiveSequence_b3) 
+                c_IoExpWriteSeq:     {Command_b3, ShReg_b8} <= #1 IoExpWriteSeq_b11;         
+                c_IoExpReadSeq:      {Command_b3, ShReg_b8} <= #1 IoExpReadSeq_b11;   
+                c_I2cSlaveRead:      {Command_b3, ShReg_b8} <= #1 I2cMuxRdSlaveRegSeq_b11; 
+                c_I2cSlaveWrite:     {Command_b3, ShReg_b8} <= #1 I2cMuxWrSlaveRegSeq_b11;  
+                default:             {Command_b3, ShReg_b8} <= #1 {c_GoToIdle, 8'h0};  
+            endcase
+        end
+        s_StartExecution : begin
+            NewByteRead_op    <= #1 1'b0;
+            BitCounter_c4     <= #1 4'h0;
+            SclCounter_c10    <= #1 10'h0;
+            if (NextState_ab4==s_GetScl0)   I2CAck      <= #1 ShReg_b8[0]; 
+        end     
+        // Start bit sequence                   
+        s_StartSda1 : begin
+            SdaOe_e <= #1 1'b0;
+            if (NextState_ab4 !=  State_qb4) SclCounter_c10    <= #1 'h0;
+            else if (Sda_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;
+        end             
+        s_StartScl1 : begin
+            SclOe_e <= #1 1'b0;
+            if (NextState_ab4 !=  State_qb4) SclCounter_c10    <= #1 'h0;
+            else if (Scl_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;        
+        end          
+        s_StartSda0 : begin
+            SdaOe_e <= #1 1'b1;
+            if (NextState_ab4 !=  State_qb4) SclCounter_c10    <= #1 'h0;
+            else if (!Sda_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;        
+        end             
+        s_StartScl0 : begin
+            SclOe_e <= #1 1'b1;
+            if (NextState_ab4 !=  State_qb4) SclCounter_c10    <= #1 'h0;
+            else if (!Scl_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;        
+        end   
+        // Byte sending sequence                              
+        s_SendScl0 : begin
+            SclOe_e             <= #1 1'b1;
+            if (NextState_ab4 !=  State_qb4) SclCounter_c10    <= #1 'h0;
+            else if (!Scl_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0; 
+            if (SclCounter_c10[8:0]==g_SclHalfPeriod[9:1])  SdaOe_e <= #1 BitCounter_c4[3] ? 1'b0 : !ShReg_b8[7];   
+        end
+        s_SendScl1 : begin
+            SclOe_e             <= #1 1'b0;
+            if (NextState_ab4 !=  State_qb4) begin
+                BitCounter_c4       <= #1 BitCounter_c4 + 1'b1;
+                SclCounter_c10    <= #1 'h0;
+                ShReg_b8[7:1]       <= #1 ShReg_b8[6:0];
+                I2CAck              <= #1 Sda_ioz; 
+            end else if (Scl_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;                          
+        end             
+       // Byte getting sequence                               
+        s_GetScl0 : begin
+            SclOe_e             <= #1 1'b1;
+            SdaOe_e             <= #1 (BitCounter_c4==4'd8) ? !I2CAck : 1'b0;        
+            if (NextState_ab4 !=  State_qb4) SclCounter_c10    <= #1 'h0;
+            else if (!Scl_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;         
+        end                              
+        s_GetScl1 : begin
+            SclOe_e             <= #1 1'b0;
+            if (NextState_ab4 !=  State_qb4) begin
+                BitCounter_c4       <= #1 BitCounter_c4 + 1'b1;
+                SclCounter_c10    <= #1 'h0;
+                ShReg_b8            <= #1 (BitCounter_c4==4'd8) ? ShReg_b8 : {ShReg_b8[6:0], Sda_ioz};         
+            end else if (Scl_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;               
+        end  
+        // Stop bit sequence                                       
+        s_StopSda0 : begin
+            SdaOe_e <= #1 1'b1;
+            if (NextState_ab4 !=  State_qb4) SclCounter_c10    <= #1 'h0;
+            else if (!Sda_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;  
+        end              
+        s_StopScl1 : begin
+            SclOe_e <= #1 1'b0;
+            if (NextState_ab4 !=  State_qb4) SclCounter_c10    <= #1 'h0;
+            else if (Scl_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;        
+        end              
+        s_StopSda1 : begin
+            SdaOe_e <= #1 1'b0;
+            if (NextState_ab4 !=  State_qb4) SclCounter_c10    <= #1 'h0;
+            else if (Sda_ioz) SclCounter_c10 <= #1 SclCounter_c10 + 1'b1;
+            else SclCounter_c10    <= #1 'h0;        
+        end  
+        // Protection from bad state condition               
+        default: begin
+            SclOe_e             <= #1 1'b0;
+            SdaOe_e             <= #1 1'b0;         
+        end
+    endcase
+ end
+    
+assign Scl_ioz = SclOe_e ? 1'b0 : 1'bz;
+assign Sda_ioz = SdaOe_e ? 1'b0 : 1'bz;
+ 
+
+endmodule
\ No newline at end of file
--- a/top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpReqArbiter.v
+++ b/top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpReqArbiter.v
+//============================================================================================\\
+//##################################   Module Information   ##################################\\
+//============================================================================================\\
+//                                                                                         
+// Company: CERN (BE-BI) 
+//                                                        
+// File Name: I2cExpAndMuxMaster.v  
+//
+// File versions history:
+//
+//       DATE          VERSION      AUTHOR             DESCRIPTION
+//     - <date>        <version>    Andrea Boccardi    <description>               
+//
+// Language: Verilog 2005                                                              
+//
+// Description:
+// 
+//      
+//
+//      At start up and after each reset the module: 
+//          - scan all the IO Exp to set them in the appropriate IO state and read the actual value
+//          - for each moddef0 to ground the SFP is access to read the ID of the module
+//      After start up the module goes trough all the external requests, in a round robin guaranteed
+//      by a mute after each access reset once no requests remains unmuted (for the BlmIn the muting can be masked):
+//          - if an IoExp has an interrupt is served with the following order
+//              -- BlmIn
+//              -- SfpApp12
+//                  --- if one of the Sfp is inserted (ModDef going to 0) the ID is read immediately
+//              -- SfpApp32
+//                  --- if one of the Sfp is inserted (ModDef going to 0) the ID is read immediately
+//              -- SfpBstEth
+//                  --- if one of the Sfp is inserted (ModDef going to 0) the ID is read immediately        
+//              -- SfpLos
+//          - if one of the Sfp settings (rateselect and disable) is changed we propagate the change
+//          - if one of the GpIo settings is changed we propagate the change
+//          - if one of the Leds settings is changed we propagate the change
+//          - if there is a request to access one I2c interface we execute it
+//      BlmIn can be set to latency deterministic mode. If this is the case a BlmIn int mutes all the requests
+//      for a time equal to the longest transaction and is than read and than the mute removed (the time is
+//      programmable)
+//  
+//
+//                                                                                                   
+//============================================================================================\\
+//############################################################################################\\
+//============================================================================================\\
+
+`timescale 1ns/100ps 
+
+module I2cExpAndMuxReqArbiter 
+//====================================  Global Parameters  ===================================\\   
+#(  parameter g_SclHalfPeriod = 10'd256)      
+//========================================  I/O ports  =======================================\\    
+
+(   
+    //==== Clocks & Resets ====\\ 
+    input             Clk_ik,
+    input             Rst_irq,
+    //==== Master interface ====\\    
+    // IO Expanders parameters:
+    output reg        IoExpWrReq_oq,    
+    input             IoExpWrOn_i,
+    output reg        IoExpRdReq_oq,     
+    input             IoExpRdOn_i,    
+    output reg  [2:0] IoExpAddr_oqb3,
+    output reg  [1:0] IoExpRegAddr_oqb2, 
+    output reg  [7:0] IoExpData_oqb8,  
+    // I2c Mux parameters:
+    output reg        I2cSlaveWrReq_oq,
+    input             I2cSlaveWrOn_i,
+    output reg        I2cSlaveRdReq_oq,
+    input             I2cSlaveRdOn_i,    
+    output reg        I2cMuxAddress_oq,
+    output reg  [1:0] I2cMuxChannel_oqb2, 
+    output reg  [6:0] I2cSlaveAddr_oqb7,
+    output reg  [7:0] I2cSlaveRegAddr_oqb8,
+    output reg  [7:0] I2cSlaveByte_oqb8,   
+    // Status and results: 
+    input             MasterBusy_i,
+    input             MasterNewByteRead_ip,
+    input       [7:0] MasterByteOut_ib8,
+    input             MasterAckError_i,
+    //==== I2c IO expander interrupts ====\\    
+    input             IoExpApp12Int_ian,
+    input             IoExpApp34Int_ian,
+    input             IoExpBstEthInt_ian,
+    input             IoExpLosInt_ian,
+    input             IoExpBlmInInt_ian,   
+    //==== System and Application Interface ====\\ 
+    output reg        InitDone_oq,
+    // Vme Ga and GaP:
+    output reg  [4:0] VmeGa_onqb5,
+    output reg        VmeGaP_onq,
+    // Leds:
+    input       [7:0] Led_ib8,
+    output reg  [7:0] StatusLed_ob8,
+    // GpIo:
+    input             GpIo1A2B_i,
+    input             EnGpIo1Term_i,
+    input             GpIo2A2B_i,
+    input             EnGpIo2Term_i,    
+    input             GpIo34A2B_i,
+    input             EnGpIo3Term_i,    
+    input             EnGpIo4Term_i,    
+    output reg        StatusGpIo1A2B_oq,
+    output reg        StatusEnGpIo1Term_oq,
+    output reg        StatusGpIo2A2B_oq,
+    output reg        StatusEnGpIo2Term_oq,    
+    output reg        StatusGpIo34A2B_oq,
+    output reg        StatusEnGpIo3Term_oq,    
+    output reg        StatusEnGpIo4Term_oq, 
+    // BlmIn:
+    output reg  [7:0] BlmIn_oqb8,
+    // AppSfp1:
+    output reg        AppSfp1Present_oq,
+    output reg [15:0] AppSfp1Id_oq16,
+    output reg        AppSfp1TxFault_oq,
+    output reg        AppSfp1Los_oq,
+    input             AppSfp1TxDisable_i,
+    input             AppSfp1RateSelect_i,
+    output reg        StatusAppSfp1TxDisable_oq,
+    output reg        StatusAppSfp1RateSelect_oq,    
+    // AppSfp2:
+    output reg        AppSfp2Present_oq,
+    output reg [15:0] AppSfp2Id_oq16,
+    output reg        AppSfp2TxFault_oq,
+    output reg        AppSfp2Los_oq,
+    input             AppSfp2TxDisable_i,
+    input             AppSfp2RateSelect_i, 
+    output reg        StatusAppSfp2TxDisable_oq,
+    output reg        StatusAppSfp2RateSelect_oq,    
+    // AppSfp3:
+    output reg        AppSfp3Present_oq,
+    output reg [15:0] AppSfp3Id_oq16,
+    output reg        AppSfp3TxFault_oq,
+    output reg        AppSfp3Los_oq,
+    input             AppSfp3TxDisable_i,
+    input             AppSfp3RateSelect_i,  
+    output reg        StatusAppSfp3TxDisable_oq,
+    output reg        StatusAppSfp3RateSelect_oq,
+    // AppSfp4:
+    output reg        AppSfp4Present_oq,
+    output reg [15:0] AppSfp4Id_oq16,
+    output reg        AppSfp4TxFault_oq,
+    output reg        AppSfp4Los_oq,
+    input             AppSfp4TxDisable_i,
+    input             AppSfp4RateSelect_i,  
+    output reg        StatusAppSfp4TxDisable_oq,
+    output reg        StatusAppSfp4RateSelect_oq,
+    // BstSfp:
+    output reg        BstSfpPresent_oq,
+    output reg [15:0] BstSfpId_oq16,
+    output reg        BstSfpTxFault_oq,
+    output reg        BstSfpLos_oq,
+    input             BstSfpTxDisable_i,
+    input             BstSfpRateSelect_i,  
+    output reg        StatusBstSfpTxDisable_oq,
+    output reg        StatusBstSfpRateSelect_oq,    
+    // EthSfp:
+    output reg        EthSfpPresent_oq,
+    output reg [15:0] EthSfpId_oq16,
+    output reg        EthSfpTxFault_oq,
+    output reg        EthSfpLos_oq,
+    input             EthSfpTxDisable_i,
+    input             EthSfpRateSelect_i, 
+    output reg        StatusEthSfpTxDisable_oq,
+    output reg        StatusEthSfpRateSelect_oq,     
+    // CDR:
+    output reg        CdrLos_oq,
+    output reg        CdrLol_oq,
+    //==== WishBone interface for the I2C slaves ====\\ 
+    input              I2cWbCyc_i,
+    input              I2cWbStb_i,
+    input              I2cWbWe_i,
+    input       [11:0] I2cWbAdr_ib12,
+    input        [7:0] I2cWbDat_ib8,
+    output  reg  [7:0] I2cWbDat_ob8,
+    output  reg        I2cWbAck_o,    
+    //==== WishBone interface for the configuration ====\\ 
+    input              WbCyc_i,
+    input              WbStb_i,
+    input              WbWe_i,
+    input       [31:0] WbDat_ib32,
+    output  reg [31:0] WbDat_oqb32,
+    output  reg        WbAck_oa    
+);     
+   
+//=======================================  Declarations  =====================================\\    
+//==== Local parameters ====\\ 
+// FSM:
+localparam  s_Idle            = 6'd00,
+            s_GaRead          = 6'd01,
+            s_BlmInRead       = 6'd02,
+            s_LosRead         = 6'd03,
+            s_GpioWrite       = 6'd04, 
+            s_GpioSetMode     = 6'd05, 
+            s_LedWrite        = 6'd06, 
+            s_LedSetMode      = 6'd07,     
+            s_BstEthWrite     = 6'd08, 
+            s_BstEthSetMode   = 6'd09, 
+            s_App1App2Write   = 6'd10, 
+            s_App1App2SetMode = 6'd11, 
+            s_App3App4Write   = 6'd12, 
+            s_App3App4SetMode = 6'd13, 
+            s_BstEthRead      = 6'd14, 
+            s_BstReadId1      = 6'd15, 
+            s_BstReadId2      = 6'd16,      
+            s_BstI2cRead      = 6'd17, 
+            s_BstI2cWrite     = 6'd18,       
+            s_EthReadId1      = 6'd19, 
+            s_EthReadId2      = 6'd20, 
+            s_EthI2cRead      = 6'd21, 
+            s_EthI2cWrite     = 6'd22, 
+            s_App1App2Read    = 6'd23, 
+            s_App1ReadId1     = 6'd24, 
+            s_App1ReadId2     = 6'd25, 
+            s_App1I2cRead     = 6'd26, 
+            s_App1I2cWrite    = 6'd27,       
+            s_App2ReadId1     = 6'd28, 
+            s_App2ReadId2     = 6'd29, 
+            s_App2I2cRead     = 6'd30, 
+            s_App2I2cWrite    = 6'd31, 
+            s_App3App4Read    = 6'd32, 
+            s_App3ReadId1     = 6'd33, 
+            s_App3ReadId2     = 6'd34, 
+            s_App3I2cRead     = 6'd35, 
+            s_App3I2cWrite    = 6'd36, 
+            s_App4ReadId1     = 6'd37, 
+            s_App4ReadId2     = 6'd38,       
+            s_App4I2cRead     = 6'd39, 
+            s_App4I2cWrite    = 6'd40, 
+            s_CdrI2cRead      = 6'd41, 
+            s_CdrI2cWrite     = 6'd42,        
+            s_Si57xI2cRead    = 6'd43, 
+            s_Si57xI2cWrite   = 6'd44; 
+ 
+//==== Wires & Regs ====\\ 
+
+reg [31:0] GlobalConfigReg_q32;
+reg [31:0] BlmInConfigReg_q32;
+reg [5:0] State_q = s_Idle, NextState_a, State_d = s_Idle;
+reg AppSfp12ExpWrReqMask, AppSfp34ExpWrReqMask, BstEthSfpExpWrReqMask, GpioExpWrReqMask, LedExpWrReqMask, AppSfp12ExpRdReqMask, AppSfp34ExpRdReqMask, BstEthSfpExpRdReqMask, LosExRdReqMask;       
+reg BlmInRdReqMask, AppSfp1I2cAccReqMask, AppSfp2I2cAccReqMask, AppSfp3I2cAccReqMask, AppSfp4I2cAccReqMask, BstSfpI2cAccReqMask, EthSfpI2cAccReqMask, CdrI2cAccReqMask, Si57xI2cAccReqMask; 
+reg [23:0] BlmInMuteOthersCnt_c24 = 0;
+reg PreAppSfp1Present_q = 0, 
+    PreAppSfp2Present_q = 0, 
+    PreAppSfp3Present_q = 0, 
+    PreAppSfp4Present_q = 0, 
+    PreEthSfpPresent_q  = 0, 
+    PreBstSfpPresent_q  = 0; 
+reg MasterBusy_d    = 0,
+    MasterTrnDone_p = 0;
+reg [2:0] IoExpApp12Int_x3, IoExpApp34Int_x3, IoExpBstEthInt_x3, IoExpLosInt_x3, IoExpBlmInInt_x3;
+reg [23:0] WaitCounter_c24 = 0;
+ 
+initial InitDone_oq = 0;
+ 
+//=======================================  User Logic  =======================================\\    
+
+//==== WishBone Interface ====\\ 
+
+always @(posedge Clk_ik) 
+    if (Rst_irq) begin
+        GlobalConfigReg_q32 <= #1 {3'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 24'd250_000}; //Comment: all int enabled and the BLMIN timeout set to 2ms (2 SFP plugged at the same time). 1ms is the more reasonable delay if we allow plugging or 500us if we don't
+        WbAck_oa            <= #1 1'b0;
+    end else begin  
+        if (WbCyc_i && WbWe_i && WbStb_i) GlobalConfigReg_q32 <= #1 GlobalConfigReg_q32;
+        WbDat_oqb32    <= #1 WbWe_i ? WbDat_ib32 : GlobalConfigReg_q32;
+        WbAck_oa       <= #1 WbStb_i&&WbCyc_i;
+    end
+ 
+wire        a_BlmInI2cIntDisable         = GlobalConfigReg_q32[28]; 
+wire        a_LosI2cIntDisable           = GlobalConfigReg_q32[27]; 
+wire        a_BstEthSfpI2cIntDisable     = GlobalConfigReg_q32[26];
+wire        a_AppSfp34I2cIntDisable      = GlobalConfigReg_q32[25];
+wire        a_AppSfp12I2cIntDisable      = GlobalConfigReg_q32[24];
+wire [23:0] a_BlmInMuteOthersTime_b24    = GlobalConfigReg_q32[23:0];  //Comment: if the timeout is 0 the BLMIN works like the others, if is !=0 than it is never muted and mutes the others to guarantee latency determinism
+wire        a_BlmInI2cIntTimeOutEnable   = |a_BlmInMuteOthersTime_b24;    
+
+
+//==== I2C Wishbone Address Decoder ====\\
+
+reg [3:0] SelectedInterface_b4 ;
+
+localparam  c_SelNothing    = 4'd0,
+            c_SelAppSfp1    = 4'd1,
+            c_SelAppSfp2    = 4'd2,
+            c_SelAppSfp3    = 4'd3,
+            c_SelAppSfp4    = 4'd4,
+            c_SelBstSfp     = 4'd5,
+            c_SelEthSfp     = 4'd6,
+            c_SelCdr        = 4'd7,
+            c_SelSi57x      = 4'd8;
+
+always @* 
+    if (I2cWbCyc_i && I2cWbStb_i && ~I2cWbAck_o) casez(I2cWbAdr_ib12)
+        12'b000?_????????: SelectedInterface_b4 = c_SelAppSfp1 ;
+        12'b001?_????????: SelectedInterface_b4 = c_SelAppSfp2 ;
+        12'b010?_????????: SelectedInterface_b4 = c_SelAppSfp3 ;
+        12'b011?_????????: SelectedInterface_b4 = c_SelAppSfp4 ;
+        12'b100?_????????: SelectedInterface_b4 = c_SelBstSfp  ;
+        12'b101?_????????: SelectedInterface_b4 = c_SelEthSfp  ;
+        12'b1100_????????: SelectedInterface_b4 = c_SelCdr     ;
+        12'b1110_????????: SelectedInterface_b4 = c_SelSi57x   ;
+        default:           SelectedInterface_b4 = c_SelNothing ;
+        endcase 
+    else SelectedInterface_b4 = c_SelNothing;
+
+//==== I2c Exp and Mux Access Requests ====\\ 
+ 
+always @(posedge Clk_ik) begin
+    IoExpApp12Int_x3  <= #1 {IoExpApp12Int_x3 [1:0], IoExpApp12Int_ian};
+    IoExpApp34Int_x3  <= #1 {IoExpApp34Int_x3 [1:0], IoExpApp34Int_ian};
+    IoExpBstEthInt_x3 <= #1 {IoExpBstEthInt_x3[1:0], IoExpBstEthInt_ian};
+    IoExpLosInt_x3    <= #1 {IoExpLosInt_x3   [1:0], IoExpLosInt_ian};
+    IoExpBlmInInt_x3  <= #1 {IoExpBlmInInt_x3 [1:0], IoExpBlmInInt_ian};
+end 
+       
+wire BlmInRdReq        = ~BlmInRdReqMask        && ~(IoExpBlmInInt_x3[2] || a_BlmInI2cIntDisable);
+wire AppSfp12ExpRdReq  = ~AppSfp12ExpRdReqMask  && ~(IoExpApp12Int_x3[2] || a_AppSfp12I2cIntDisable);
+wire AppSfp34ExpRdReq  = ~AppSfp34ExpRdReqMask  && ~(IoExpApp34Int_x3[2] || a_AppSfp34I2cIntDisable);
+wire BstEthSfpExpRdReq = ~BstEthSfpExpRdReqMask && ~(IoExpBstEthInt_x3[2] || a_BstEthSfpI2cIntDisable);
+wire LosExRdReq        = ~LosExRdReqMask        && ~(IoExpLosInt_x3[2] || a_LosI2cIntDisable);
+wire AppSfp12ExpWrReq  = ~AppSfp12ExpWrReqMask  && (AppSfp1TxDisable_i^StatusAppSfp1TxDisable_oq) || (AppSfp1RateSelect_i^StatusAppSfp1RateSelect_oq) || (AppSfp2TxDisable_i^StatusAppSfp2TxDisable_oq) || (AppSfp2RateSelect_i^StatusAppSfp2RateSelect_oq);
+wire AppSfp34ExpWrReq  = ~AppSfp34ExpWrReqMask  && (AppSfp3TxDisable_i^StatusAppSfp3TxDisable_oq) || (AppSfp3RateSelect_i^StatusAppSfp3RateSelect_oq) || (AppSfp4TxDisable_i^StatusAppSfp4TxDisable_oq) || (AppSfp4RateSelect_i^StatusAppSfp4RateSelect_oq);
+wire BstEthSfpExpWrReq = ~BstEthSfpExpWrReqMask && (BstSfpTxDisable_i^StatusBstSfpTxDisable_oq) || (BstSfpRateSelect_i^StatusBstSfpRateSelect_oq) || (EthSfpTxDisable_i^StatusEthSfpTxDisable_oq) || (EthSfpRateSelect_i^StatusEthSfpRateSelect_oq);
+wire GpioExpWrReq      = ~GpioExpWrReqMask      && (GpIo1A2B_i^StatusGpIo1A2B_oq || EnGpIo1Term_i^StatusEnGpIo1Term_oq || GpIo2A2B_i^StatusGpIo2A2B_oq || EnGpIo2Term_i^StatusEnGpIo2Term_oq || GpIo34A2B_i^StatusGpIo34A2B_oq || EnGpIo3Term_i^StatusEnGpIo3Term_oq || EnGpIo4Term_i^StatusEnGpIo4Term_oq);    
+wire LedExpWrReq       = ~LedExpWrReqMask       && (Led_ib8!=StatusLed_ob8);
+
+wire AppSfp1I2cAccReq  = ~AppSfp1I2cAccReqMask  && SelectedInterface_b4 == c_SelAppSfp1;
+wire AppSfp2I2cAccReq  = ~AppSfp2I2cAccReqMask  && SelectedInterface_b4 == c_SelAppSfp2;
+wire AppSfp3I2cAccReq  = ~AppSfp3I2cAccReqMask  && SelectedInterface_b4 == c_SelAppSfp3;
+wire AppSfp4I2cAccReq  = ~AppSfp4I2cAccReqMask  && SelectedInterface_b4 == c_SelAppSfp4;
+wire BstSfpI2cAccReq   = ~BstSfpI2cAccReqMask   && SelectedInterface_b4 == c_SelBstSfp;
+wire EthSfpI2cAccReq   = ~EthSfpI2cAccReqMask   && SelectedInterface_b4 == c_SelEthSfp;
+wire CdrI2cAccReq      = ~CdrI2cAccReqMask      && SelectedInterface_b4 == c_SelCdr;
+wire Si57xI2cAccReq    = ~Si57xI2cAccReqMask    && SelectedInterface_b4 == c_SelSi57x;
+
+//==== I2c Exp and Mux End of transaction detection ====\\
+
+always @(posedge Clk_ik) MasterBusy_d    <= MasterBusy_i;
+always @(posedge Clk_ik) MasterTrnDone_p <= MasterBusy_d && ~MasterBusy_i;
+
+//==== State Machine ====\\ 
+
+always @(posedge Clk_ik) State_d <= #1 State_q;
+
+always @(posedge Clk_ik) State_q <= #1 Rst_irq ?  s_Idle :  NextState_a;
+ 
+always @* begin
+    NextState_a = State_q;
+    case (State_q)
+    s_Idle            : if (~MasterBusy_i) begin
+                            if (~InitDone_oq) NextState_a = s_GaRead;
+                            else if (|BlmInMuteOthersCnt_c24) begin  //Comment: a BlmIn int triggered a mute all to assure the latency determinism of its readout
+                                if ((BlmInMuteOthersCnt_c24 == a_BlmInMuteOthersTime_b24) && BlmInRdReq ) NextState_a = s_BlmInRead;
+                            end else begin
+                                if (BlmInRdReq && ~|a_BlmInMuteOthersTime_b24) NextState_a = s_BlmInRead; //comment: The MuteOthers is set to 0 so no need to wait
+                                else if (AppSfp12ExpRdReq )                    NextState_a = s_App1App2Read;
+                                else if (AppSfp34ExpRdReq )                    NextState_a = s_App3App4Read;
+                                else if (BstEthSfpExpRdReq)                    NextState_a = s_BstEthRead;
+                                else if (LosExRdReq       )                    NextState_a = s_LosRead;
+                                else if (AppSfp12ExpWrReq )                    NextState_a = s_App1App2Write;
+                                else if (AppSfp34ExpWrReq )                    NextState_a = s_App3App4Write;
+                                else if (BstEthSfpExpWrReq)                    NextState_a = s_BstEthWrite;
+                                else if (GpioExpWrReq     )                    NextState_a = s_GpioWrite;
+                                else if (LedExpWrReq      )                    NextState_a = s_LedWrite;
+                                else if (AppSfp1I2cAccReq )                    NextState_a = I2cWbWe_i ? s_App1I2cWrite  : s_App1I2cRead; 
+                                else if (AppSfp2I2cAccReq )                    NextState_a = I2cWbWe_i ? s_App2I2cWrite  : s_App2I2cRead; 
+                                else if (AppSfp3I2cAccReq )                    NextState_a = I2cWbWe_i ? s_App3I2cWrite  : s_App3I2cRead; 
+                                else if (AppSfp4I2cAccReq )                    NextState_a = I2cWbWe_i ? s_App4I2cWrite  : s_App4I2cRead; 
+                                else if (BstSfpI2cAccReq  )                    NextState_a = I2cWbWe_i ? s_BstI2cWrite   : s_BstI2cRead; 
+                                else if (EthSfpI2cAccReq  )                    NextState_a = I2cWbWe_i ? s_EthI2cWrite   : s_EthI2cRead;
+                                else if (CdrI2cAccReq     )                    NextState_a = I2cWbWe_i ? s_CdrI2cWrite   : s_CdrI2cRead;
+                                else if (Si57xI2cAccReq   )                    NextState_a = I2cWbWe_i ? s_Si57xI2cWrite : s_Si57xI2cRead;
+                            end   
+                        end
+    s_GaRead          : if (MasterTrnDone_p) NextState_a = s_BlmInRead; //Comment: this is executed only in the initialization sequence
+    s_BlmInRead       : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_LosRead        ;
+    s_LosRead         : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_GpioWrite      ;
+    s_GpioWrite       : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_GpioSetMode    ;
+    s_GpioSetMode     : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_LedWrite       ;
+    s_LedWrite        : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_LedSetMode     ;
+    s_LedSetMode      : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_BstEthWrite    ;
+    s_BstEthWrite     : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_BstEthSetMode  ;   
+    s_BstEthSetMode   : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_App1App2Write  ;
+    s_App1App2Write   : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_App1App2SetMode;
+    s_App1App2SetMode : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_App3App4Write  ;
+    s_App3App4Write   : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_App3App4SetMode;
+    s_App3App4SetMode : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_BstEthRead     ;
+    s_BstEthRead      : if (MasterTrnDone_p) begin
+                            if      (PreBstSfpPresent_q && ~BstSfpPresent_oq) NextState_a = s_BstReadId1;
+                            else if (PreEthSfpPresent_q && ~EthSfpPresent_oq) NextState_a = s_EthReadId1;
+                            else                                              NextState_a = InitDone_oq ? s_Idle : s_App1App2Read;
+                        end
+    s_BstReadId1      : if (MasterTrnDone_p) NextState_a = s_BstReadId2;
+    s_BstReadId2      : if (MasterTrnDone_p) begin
+                            if (PreEthSfpPresent_q && ~EthSfpPresent_oq) NextState_a = s_EthReadId1;
+                            else                                         NextState_a = InitDone_oq ? s_Idle : s_App1App2Read;
+                        end
+    s_EthReadId1      : if (MasterTrnDone_p) NextState_a = s_EthReadId2;
+    s_EthReadId2      : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_App1App2Read;
+    s_App1App2Read    : if (MasterTrnDone_p) begin
+                            if      (PreAppSfp1Present_q && ~AppSfp1Present_oq) NextState_a = s_App1ReadId1;
+                            else if (PreAppSfp2Present_q && ~AppSfp2Present_oq) NextState_a = s_App2ReadId1;
+                            else                                               NextState_a = InitDone_oq ? s_Idle : s_App3App4Read;
+                        end
+    s_App1ReadId1     : if (MasterTrnDone_p) NextState_a = s_App1ReadId2;
+    s_App1ReadId2     : if (MasterTrnDone_p) begin
+                            if (PreAppSfp2Present_q && ~AppSfp2Present_oq) NextState_a = s_App2ReadId1;
+                            else                                          NextState_a = InitDone_oq ? s_Idle : s_App3App4Read;
+                        end   
+    s_App2ReadId1     : if (MasterTrnDone_p) NextState_a = s_App2ReadId2;
+    s_App2ReadId2     : if (MasterTrnDone_p) NextState_a = InitDone_oq ? s_Idle : s_App3App4Read;  
+    s_App3App4Read    : if (MasterTrnDone_p) begin
+                            if      (PreAppSfp3Present_q && ~AppSfp3Present_oq) NextState_a = s_App3ReadId1;
+                            else if (PreAppSfp4Present_q && ~AppSfp4Present_oq) NextState_a = s_App4ReadId1;
+                            else                                               NextState_a = s_Idle;
+                        end
+    s_App3ReadId1     : if (MasterTrnDone_p) NextState_a = s_App3ReadId2;
+    s_App3ReadId2     : if (MasterTrnDone_p) begin
+                            if (PreAppSfp4Present_q && ~AppSfp4Present_oq) NextState_a = s_App4ReadId1;
+                            else                                          NextState_a = s_Idle;
+                        end   
+    s_App4ReadId1     : if (MasterTrnDone_p) NextState_a = s_App4ReadId2;
+    s_App4ReadId2     : if (MasterTrnDone_p) NextState_a = s_Idle; 
+    s_BstI2cRead      : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_BstI2cWrite     : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_EthI2cRead      : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_EthI2cWrite     : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_App1I2cRead     : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_App1I2cWrite    : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_App2I2cRead     : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_App2I2cWrite    : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_App3I2cRead     : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_App3I2cWrite    : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_App4I2cRead     : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_App4I2cWrite    : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle; 
+    s_CdrI2cRead      : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_CdrI2cWrite     : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_Si57xI2cRead    : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    s_Si57xI2cWrite   : if (~(I2cWbCyc_i && I2cWbStb_i)) NextState_a = s_Idle;
+    endcase
+end
+    
+always @(posedge Clk_ik) begin
+    if (Rst_irq) begin
+        InitDone_oq                <= #1 1'b0;
+        IoExpWrReq_oq              <= #1 1'b0;    
+        IoExpRdReq_oq              <= #1 1'b0;     
+        IoExpAddr_oqb3             <= #1 3'b0;
+        IoExpRegAddr_oqb2          <= #1 2'b0; 
+        IoExpData_oqb8             <= #1 8'b0;  
+        I2cSlaveWrReq_oq           <= #1 1'b0;
+        I2cSlaveRdReq_oq           <= #1 1'b0;
+        I2cMuxAddress_oq           <= #1 1'b0;
+        I2cMuxChannel_oqb2         <= #1 2'b0; 
+        I2cSlaveAddr_oqb7          <= #1 7'b0;
+        I2cSlaveRegAddr_oqb8       <= #1 8'b0;
+        I2cSlaveByte_oqb8          <= #1 8'b0;      
+        VmeGa_onqb5                <= #1 5'b0;
+        VmeGaP_onq                 <= #1 1'b0;
+        StatusLed_ob8              <= #1 8'b0;
+        StatusGpIo1A2B_oq          <= #1 1'b0;
+        StatusEnGpIo1Term_oq       <= #1 1'b0;
+        StatusGpIo2A2B_oq          <= #1 1'b0;
+        StatusEnGpIo2Term_oq       <= #1 1'b0;    
+        StatusGpIo34A2B_oq         <= #1 1'b0;
+        StatusEnGpIo3Term_oq       <= #1 1'b0;    
+        StatusEnGpIo4Term_oq       <= #1 1'b0; 
+        BlmIn_oqb8                 <= #1 8'b0;
+        AppSfp1Present_oq          <= #1 1'b0;
+        AppSfp1Id_oq16             <= #1 16'b0;
+        AppSfp1TxFault_oq          <= #1 1'b0;
+        AppSfp1Los_oq              <= #1 1'b0;
+        StatusAppSfp1TxDisable_oq  <= #1 1'b0;
+        StatusAppSfp1RateSelect_oq <= #1 1'b0;    
+        AppSfp2Present_oq          <= #1 1'b0;
+        AppSfp2Id_oq16             <= #1 16'b0;
+        AppSfp2TxFault_oq          <= #1 1'b0;
+        AppSfp2Los_oq              <= #1 1'b0;
+        StatusAppSfp2TxDisable_oq  <= #1 1'b0;
+        StatusAppSfp2RateSelect_oq <= #1 1'b0;    
+        AppSfp3Present_oq          <= #1 1'b0;
+        AppSfp3Id_oq16             <= #1 16'b0;
+        AppSfp3TxFault_oq          <= #1 1'b0;
+        AppSfp3Los_oq              <= #1 1'b0;
+        StatusAppSfp3TxDisable_oq  <= #1 1'b0;
+        StatusAppSfp3RateSelect_oq <= #1 1'b0; 
+        AppSfp4Present_oq          <= #1 1'b0;
+        AppSfp4Id_oq16             <= #1 16'b0;
+        AppSfp4TxFault_oq          <= #1 1'b0;
+        AppSfp4Los_oq              <= #1 1'b0;
+        StatusAppSfp4TxDisable_oq  <= #1 1'b0;
+        StatusAppSfp4RateSelect_oq <= #1 1'b0; 
+        BstSfpPresent_oq           <= #1 1'b0;
+        BstSfpId_oq16              <= #1 16'b0;
+        BstSfpTxFault_oq           <= #1 1'b0;
+        BstSfpLos_oq               <= #1 1'b0;
+        StatusBstSfpTxDisable_oq   <= #1 1'b0;
+        StatusBstSfpRateSelect_oq  <= #1 1'b0;    
+        EthSfpPresent_oq           <= #1 1'b0;
+        EthSfpId_oq16              <= #1 16'b0;
+        EthSfpTxFault_oq           <= #1 1'b0;
+        EthSfpLos_oq               <= #1 1'b0;
+        StatusEthSfpTxDisable_oq   <= #1 1'b0;
+        StatusEthSfpRateSelect_oq  <= #1 1'b0;     
+        CdrLos_oq                  <= #1 1'b0;
+        CdrLol_oq                  <= #1 1'b1;
+        BlmInRdReqMask             <= #1 1'b0;
+        AppSfp12ExpRdReqMask       <= #1 1'b0;
+        AppSfp34ExpRdReqMask       <= #1 1'b0;
+        BstEthSfpExpRdReqMask      <= #1 1'b0;
+        LosExRdReqMask             <= #1 1'b0;
+        AppSfp12ExpWrReqMask       <= #1 1'b0;
+        AppSfp34ExpWrReqMask       <= #1 1'b0;
+        BstEthSfpExpWrReqMask      <= #1 1'b0;
+        GpioExpWrReqMask           <= #1 1'b0;
+        LedExpWrReqMask            <= #1 1'b0;
+        AppSfp1I2cAccReqMask       <= #1 1'b0;
+        AppSfp2I2cAccReqMask       <= #1 1'b0;
+        AppSfp3I2cAccReqMask       <= #1 1'b0;
+        AppSfp4I2cAccReqMask       <= #1 1'b0;
+        BstSfpI2cAccReqMask        <= #1 1'b0;
+        EthSfpI2cAccReqMask        <= #1 1'b0;
+        CdrI2cAccReqMask           <= #1 1'b0;
+        Si57xI2cAccReqMask         <= #1 1'b0;
+        BlmInMuteOthersCnt_c24     <= #1 24'h0;
+        PreAppSfp1Present_q        <= #1 1'b0; 
+        PreAppSfp2Present_q        <= #1 1'b0; 
+        PreAppSfp3Present_q        <= #1 1'b0; 
+        PreAppSfp4Present_q        <= #1 1'b0; 
+        PreEthSfpPresent_q         <= #1 1'b0; 
+        PreBstSfpPresent_q         <= #1 1'b0;  
+        I2cWbAck_o                 <= #1 1'b0;
+        WaitCounter_c24            <= #1 24'h0;
+    end else begin
+        if (~InitDone_oq || ~a_BlmInI2cIntTimeOutEnable) BlmInMuteOthersCnt_c24 <= #1 24'h0;
+        else if (|BlmInMuteOthersCnt_c24 || (BlmInRdReq && |a_BlmInMuteOthersTime_b24)) BlmInMuteOthersCnt_c24 <= #1 BlmInMuteOthersCnt_c24 + 1'b1;      
+        case(State_q)
+        s_Idle            : begin 
+            I2cWbAck_o                 <= #1 1'b0;
+            WaitCounter_c24            <= #1 24'h0;
+            if (~(BlmInRdReq||AppSfp12ExpRdReq||AppSfp34ExpRdReq||BstEthSfpExpRdReq||LosExRdReq||AppSfp12ExpWrReq||AppSfp34ExpWrReq||BstEthSfpExpWrReq||GpioExpWrReq||LedExpWrReq||AppSfp1I2cAccReq||AppSfp2I2cAccReq||AppSfp3I2cAccReq ||AppSfp4I2cAccReq||BstSfpI2cAccReq||EthSfpI2cAccReq||CdrI2cAccReq||Si57xI2cAccReq)) begin
+                BlmInRdReqMask             <= #1 1'b0;
+                AppSfp12ExpRdReqMask       <= #1 1'b0;
+                AppSfp34ExpRdReqMask       <= #1 1'b0;
+                BstEthSfpExpRdReqMask      <= #1 1'b0;
+                LosExRdReqMask             <= #1 1'b0;
+                AppSfp12ExpWrReqMask       <= #1 1'b0;
+                AppSfp34ExpWrReqMask       <= #1 1'b0;
+                BstEthSfpExpWrReqMask      <= #1 1'b0;
+                GpioExpWrReqMask           <= #1 1'b0;
+                LedExpWrReqMask            <= #1 1'b0;
+                AppSfp1I2cAccReqMask       <= #1 1'b0;
+                AppSfp2I2cAccReqMask       <= #1 1'b0;
+                AppSfp3I2cAccReqMask       <= #1 1'b0;
+                AppSfp4I2cAccReqMask       <= #1 1'b0;
+                BstSfpI2cAccReqMask        <= #1 1'b0;
+                EthSfpI2cAccReqMask        <= #1 1'b0;
+                CdrI2cAccReqMask           <= #1 1'b0;
+                Si57xI2cAccReqMask         <= #1 1'b0;           
+            end
+        end             
+        s_GaRead          : begin
+            if (State_q!=State_d) IoExpRdReq_oq <= #1 1'b1; 
+            else if (IoExpRdOn_i) IoExpRdReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b011;
+            IoExpRegAddr_oqb2         <= #1 2'b00; 
+            if (MasterNewByteRead_ip) {VmeGaP_onq, VmeGa_onqb5} <= #1 MasterByteOut_ib8[5:0];
+        end
+        s_BlmInRead       : begin
+            if (State_q!=State_d) IoExpRdReq_oq <= #1 1'b1; 
+            else if (IoExpRdOn_i) IoExpRdReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b110;
+            IoExpRegAddr_oqb2         <= #1 2'b00; 
+            if (MasterNewByteRead_ip) BlmIn_oqb8 <= #1 MasterByteOut_ib8;
+            BlmInRdReqMask         <= #1 ~a_BlmInI2cIntTimeOutEnable;
+            BlmInMuteOthersCnt_c24 <= #1 24'b0;
+        end
+        s_LosRead         : begin
+            if (State_q!=State_d) IoExpRdReq_oq <= #1 1'b1; 
+            else if (IoExpRdOn_i) IoExpRdReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b111;
+            IoExpRegAddr_oqb2         <= #1 2'b00; 
+            if (MasterNewByteRead_ip) {CdrLol_oq, CdrLos_oq, EthSfpLos_oq, BstSfpLos_oq, AppSfp4Los_oq, AppSfp3Los_oq, AppSfp2Los_oq, AppSfp1Los_oq} <= #1 MasterByteOut_ib8;
+            LosExRdReqMask         <= #1 1'b1;
+        end
+        s_GpioWrite       : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+                IoExpData_oqb8 <= #1 {1'b0, EnGpIo4Term_i, EnGpIo3Term_i, EnGpIo2Term_i, EnGpIo1Term_i, GpIo34A2B_i, GpIo2A2B_i, GpIo1A2B_i};
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b100;
+            IoExpRegAddr_oqb2         <= #1 2'b01;             
+            if (NextState_a != s_GpioWrite) {StatusEnGpIo4Term_oq, StatusEnGpIo3Term_oq, StatusEnGpIo2Term_oq, StatusEnGpIo1Term_oq, StatusGpIo34A2B_oq, StatusGpIo2A2B_oq, StatusGpIo1A2B_oq} <= #1 IoExpData_oqb8[6:0];
+            GpioExpWrReqMask         <= #1 1'b1;
+        end
+        s_GpioSetMode     : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+                IoExpData_oqb8 <= #1 8'b0;
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b100;
+            IoExpRegAddr_oqb2         <= #1 2'b11;             
+        end
+        s_LedWrite        : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+                IoExpData_oqb8 <= #1 ~Led_ib8;
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b101;
+            IoExpRegAddr_oqb2         <= #1 2'b01;             
+            if (NextState_a != s_LedWrite) StatusLed_ob8 <= #1 ~IoExpData_oqb8;
+            LedExpWrReqMask         <= #1 1'b1;
+        end
+        s_LedSetMode      : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+                IoExpData_oqb8 <= #1 8'b0;
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b101;
+            IoExpRegAddr_oqb2         <= #1 2'b11;             
+        end        
+        s_BstEthWrite     : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+                IoExpData_oqb8 <= #1 {1'b0, EthSfpRateSelect_i, EthSfpTxDisable_i, 1'b0, 1'b0, BstSfpRateSelect_i, BstSfpTxDisable_i, 1'b0};
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b010;
+            IoExpRegAddr_oqb2         <= #1 2'b01;             
+            if (NextState_a != s_BstEthWrite) begin
+                StatusEthSfpRateSelect_oq <= #1 IoExpData_oqb8[6];
+                StatusEthSfpTxDisable_oq  <= #1 IoExpData_oqb8[5];
+                StatusBstSfpRateSelect_oq <= #1 IoExpData_oqb8[2];
+                StatusBstSfpTxDisable_oq  <= #1 IoExpData_oqb8[1];
+            end    
+            BstEthSfpExpWrReqMask         <= #1 1'b1;
+        end
+        s_BstEthSetMode   : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b010;
+            IoExpRegAddr_oqb2         <= #1 2'b11; 
+            IoExpData_oqb8            <= #1 8'b10011001;            
+        end
+        s_BstEthRead      : begin
+            if (State_q!=State_d) IoExpRdReq_oq <= #1 1'b1; 
+            else if (IoExpRdOn_i) IoExpRdReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b010;
+            IoExpRegAddr_oqb2         <= #1 2'b00; 
+            if (MasterNewByteRead_ip) begin
+                if (MasterByteOut_ib8[7]) begin
+                    EthSfpPresent_oq <= #1 1'b0;
+                    EthSfpId_oq16    <= #1 16'h0;
+                end  
+                PreEthSfpPresent_q <= #1 ~MasterByteOut_ib8[7]; 
+                EthSfpTxFault_oq   <= #1 MasterByteOut_ib8[4];
+                if (MasterByteOut_ib8[3]) begin
+                    BstSfpPresent_oq <= #1 1'b0;
+                    BstSfpId_oq16    <= #1 16'h0;
+                end  
+                PreBstSfpPresent_q  <= #1 ~MasterByteOut_ib8[3];
+                BstSfpTxFault_oq    <= #1 MasterByteOut_ib8[0];
+            end       
+            BstEthSfpExpRdReqMask  <= #1 1'b1;
+        end
+        s_BstReadId1      : begin
+            if ((State_q!=State_d) || |WaitCounter_c24)   WaitCounter_c24  <= #1 WaitCounter_c24 + 1'b1;
+            if (&WaitCounter_c24)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0;         
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b00; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b0;
+            if (MasterNewByteRead_ip) BstSfpId_oq16[7:0] <= #1 MasterByteOut_ib8; 
+        end
+        s_BstReadId2      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0;       
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b00; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b1;
+            if (MasterNewByteRead_ip) begin 
+                BstSfpId_oq16[15:8] <= #1 MasterByteOut_ib8;
+                BstSfpPresent_oq    <= #1 1'b1;
+            end
+        end   
+        s_EthReadId1      : begin
+            if ((State_q!=State_d) || |WaitCounter_c24)   WaitCounter_c24  <= #1 WaitCounter_c24 + 1'b1;
+            if (&WaitCounter_c24)    I2cSlaveRdReq_oq <= #1 1'b1;            
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0;         
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b01; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b0;
+            if (MasterNewByteRead_ip) EthSfpId_oq16[7:0] <= #1 MasterByteOut_ib8; 
+        end
+        s_EthReadId2      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0;         
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b01; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b1;
+            if (MasterNewByteRead_ip) begin 
+                EthSfpId_oq16[15:8] <= #1 MasterByteOut_ib8;
+                EthSfpPresent_oq    <= #1 1'b1;
+            end
+        end 
+        s_App1App2Write     : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+                IoExpData_oqb8 <= #1 {1'b0, AppSfp2RateSelect_i, AppSfp2TxDisable_i, 1'b0, 1'b0, AppSfp1RateSelect_i, AppSfp1TxDisable_i, 1'b0};
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b000;
+            IoExpRegAddr_oqb2         <= #1 2'b01;             
+            if (NextState_a != s_App1App2Write) begin
+                StatusAppSfp2RateSelect_oq <= #1 IoExpData_oqb8[6];
+                StatusAppSfp2TxDisable_oq  <= #1 IoExpData_oqb8[5];
+                StatusAppSfp1RateSelect_oq <= #1 IoExpData_oqb8[2];
+                StatusAppSfp1TxDisable_oq  <= #1 IoExpData_oqb8[1];
+            end    
+            AppSfp12ExpWrReqMask         <= #1 1'b1;
+        end
+        s_App1App2SetMode   : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b000;
+            IoExpRegAddr_oqb2         <= #1 2'b11;
+            IoExpData_oqb8            <= #1 8'b10011001;            
+        end
+        s_App1App2Read      : begin
+            if (State_q!=State_d) IoExpRdReq_oq <= #1 1'b1; 
+            else if (IoExpRdOn_i) IoExpRdReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3          <= #1 3'b000;
+            IoExpRegAddr_oqb2       <= #1 2'b00; 
+            if (MasterNewByteRead_ip) begin
+                if (MasterByteOut_ib8[7]) begin
+                    AppSfp2Present_oq <= #1 1'b0;
+                    AppSfp2Id_oq16    <= #1 16'h0;
+                end 
+                PreAppSfp2Present_q <= #1 ~MasterByteOut_ib8[7]; 
+                AppSfp2TxFault_oq   <= #1 MasterByteOut_ib8[4];
+                if (MasterByteOut_ib8[3]) begin
+                    AppSfp1Present_oq <= #1 1'b0;
+                    AppSfp1Id_oq16    <= #1 16'h0;
+                end 
+                PreAppSfp1Present_q <= #1 ~MasterByteOut_ib8[3];
+                AppSfp1TxFault_oq   <= #1 MasterByteOut_ib8[0];
+            end    
+            AppSfp12ExpRdReqMask    <= #1 1'b1;
+        end
+        s_App1ReadId1      : begin
+            if ((State_q!=State_d) || |WaitCounter_c24)   WaitCounter_c24  <= #1 WaitCounter_c24 + 1'b1;
+            if (&WaitCounter_c24)    I2cSlaveRdReq_oq <= #1 1'b1;             
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0;         
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b00; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b0;
+            if (MasterNewByteRead_ip) AppSfp1Id_oq16[7:0] <= #1 MasterByteOut_ib8; 
+        end        
+        s_App1ReadId2      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0;     
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b00; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b1;
+            if (MasterNewByteRead_ip) begin 
+                AppSfp1Id_oq16[15:8]  <= #1 MasterByteOut_ib8;
+                AppSfp1Present_oq     <= #1 1'b1;
+            end
+        end  
+        s_App2ReadId1      : begin
+            if ((State_q!=State_d) || |WaitCounter_c24)   WaitCounter_c24  <= #1 WaitCounter_c24 + 1'b1;
+            if (&WaitCounter_c24)    I2cSlaveRdReq_oq <= #1 1'b1;             
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0;        
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b01; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b0;
+            if (MasterNewByteRead_ip) AppSfp2Id_oq16[7:0] <= #1 MasterByteOut_ib8; 
+        end        
+        s_App2ReadId2      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0;
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b01; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b1;
+            if (MasterNewByteRead_ip) begin 
+                AppSfp2Id_oq16[15:8] <= #1 MasterByteOut_ib8;
+                AppSfp2Present_oq    <= #1 1'b1;
+            end
+        end 
+        s_App3App4Write     : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+                IoExpData_oqb8 <= #1 {1'b0, AppSfp4RateSelect_i, AppSfp4TxDisable_i, 1'b0, 1'b0, AppSfp3RateSelect_i, AppSfp3TxDisable_i, 1'b0};
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b001;
+            IoExpRegAddr_oqb2         <= #1 2'b01;             
+            if (NextState_a != s_App1App2Write) begin
+                StatusAppSfp4RateSelect_oq <= #1 IoExpData_oqb8[6];
+                StatusAppSfp4TxDisable_oq  <= #1 IoExpData_oqb8[5];
+                StatusAppSfp3RateSelect_oq <= #1 IoExpData_oqb8[2];
+                StatusAppSfp3TxDisable_oq  <= #1 IoExpData_oqb8[1];
+            end    
+            AppSfp34ExpWrReqMask     <= #1 1'b1;
+        end
+        s_App3App4SetMode   : begin
+            if (State_q!=State_d) begin 
+                IoExpWrReq_oq  <= #1 1'b1; 
+            end else if (IoExpWrOn_i) IoExpWrReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b001;
+            IoExpRegAddr_oqb2         <= #1 2'b11; 
+            IoExpData_oqb8            <= #1 8'b10011001;            
+        end       
+        s_App3App4Read      : begin
+            if (State_q!=State_d) IoExpRdReq_oq <= #1 1'b1; 
+            else if (IoExpRdOn_i) IoExpRdReq_oq <= #1 1'b0; 
+            IoExpAddr_oqb3            <= #1 3'b001;
+            IoExpRegAddr_oqb2         <= #1 2'b00; 
+            if (MasterNewByteRead_ip) begin
+                if (MasterByteOut_ib8[7]) begin
+                    AppSfp4Present_oq <= #1 1'b0;
+                    AppSfp4Id_oq16    <= #1 16'h0;
+                end 
+                PreAppSfp4Present_q <= #1 ~MasterByteOut_ib8[7]; 
+                AppSfp4TxFault_oq   <= #1 MasterByteOut_ib8[4];
+                if (MasterByteOut_ib8[3]) begin
+                    AppSfp3Present_oq <= #1 1'b0;
+                    AppSfp3Id_oq16    <= #1 16'h0;
+                end 
+                PreAppSfp3Present_q <= #1 ~MasterByteOut_ib8[3];
+                AppSfp3TxFault_oq   <= #1 MasterByteOut_ib8[0];
+            end    
+            AppSfp34ExpRdReqMask  <= #1 1'b1;
+            if (NextState_a==s_Idle) InitDone_oq           <= #1 1'b1;
+        end
+        s_App3ReadId1      : begin
+            if ((State_q!=State_d) || |WaitCounter_c24)   WaitCounter_c24  <= #1 WaitCounter_c24 + 1'b1;
+            if (&WaitCounter_c24)    I2cSlaveRdReq_oq <= #1 1'b1;             
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b10; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b0;
+            if (MasterNewByteRead_ip) AppSfp3Id_oq16[7:0] <= #1 MasterByteOut_ib8; 
+        end        
+        s_App3ReadId2      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b10; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b1;
+            if (MasterNewByteRead_ip) begin 
+                AppSfp3Id_oq16[15:8] <= #1 MasterByteOut_ib8;
+                AppSfp3Present_oq    <= #1 1'b1;
+            end
+            if (NextState_a==s_Idle) InitDone_oq           <= #1 1'b1;            
+        end  
+        s_App4ReadId1      : begin
+            if ((State_q!=State_d) || |WaitCounter_c24)   WaitCounter_c24  <= #1 WaitCounter_c24 + 1'b1;
+            if (&WaitCounter_c24)    I2cSlaveRdReq_oq <= #1 1'b1;             
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b11; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b0;
+            if (MasterNewByteRead_ip) AppSfp4Id_oq16[7:0] <= #1 MasterByteOut_ib8; 
+        end        
+        s_App4ReadId2      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1;
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0;
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b11; 
+            I2cSlaveAddr_oqb7         <= #1 7'h50;
+            I2cSlaveRegAddr_oqb8      <= #1 8'b1;
+            if (MasterNewByteRead_ip) begin 
+                AppSfp4Id_oq16[15:8] <= #1 MasterByteOut_ib8;
+                AppSfp4Present_oq    <= #1 1'b1;
+            end
+            if (NextState_a==s_Idle) InitDone_oq <= #1 1'b1;
+        end     
+        s_BstI2cRead      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b00; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            if (MasterNewByteRead_ip) I2cWbDat_ob8 <= #1 MasterByteOut_ib8;
+            BstSfpI2cAccReqMask        <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_BstI2cWrite     : begin
+            if (State_q!=State_d)    I2cSlaveWrReq_oq <= #1 1'b1; 
+            else if (I2cSlaveWrOn_i) I2cSlaveWrReq_oq <= #1 1'b0; 
+            I2cSlaveByte_oqb8         <= #1 I2cWbDat_ib8;
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b00; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            BstSfpI2cAccReqMask       <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_EthI2cRead      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b01; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            if (MasterNewByteRead_ip) I2cWbDat_ob8 <= #1 MasterByteOut_ib8;
+            EthSfpI2cAccReqMask        <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_EthI2cWrite     : begin
+            if (State_q!=State_d)    I2cSlaveWrReq_oq <= #1 1'b1; 
+            else if (I2cSlaveWrOn_i) I2cSlaveWrReq_oq <= #1 1'b0; 
+            I2cSlaveByte_oqb8         <= #1 I2cWbDat_ib8;
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b01; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            EthSfpI2cAccReqMask       <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end        
+        s_Si57xI2cRead      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b10; 
+            I2cSlaveAddr_oqb7         <= #1 7'h55;
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            if (MasterNewByteRead_ip) I2cWbDat_ob8 <= #1 MasterByteOut_ib8;
+            Si57xI2cAccReqMask        <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_Si57xI2cWrite     : begin
+            if (State_q!=State_d)    I2cSlaveWrReq_oq <= #1 1'b1; 
+            else if (I2cSlaveWrOn_i) I2cSlaveWrReq_oq <= #1 1'b0; 
+            I2cSlaveByte_oqb8         <= #1 I2cWbDat_ib8;            
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b10; 
+            I2cSlaveAddr_oqb7         <= #1 7'h55;
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            Si57xI2cAccReqMask        <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_CdrI2cRead      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b11; 
+            I2cSlaveAddr_oqb7         <= #1 7'h40;
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            if (MasterNewByteRead_ip) I2cWbDat_ob8     <= #1 MasterByteOut_ib8;
+            CdrI2cAccReqMask          <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_CdrI2cWrite     : begin
+            if (State_q!=State_d)    I2cSlaveWrReq_oq <= #1 1'b1; 
+            else if (I2cSlaveWrOn_i) I2cSlaveWrReq_oq <= #1 1'b0; 
+            I2cSlaveByte_oqb8         <= #1 I2cWbDat_ib8;            
+            I2cMuxAddress_oq          <= #1 1'b1;
+            I2cMuxChannel_oqb2        <= #1 2'b11; 
+            I2cSlaveAddr_oqb7         <= #1 7'h40;
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            CdrI2cAccReqMask          <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end
+        s_App1I2cRead      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b00; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            if (MasterNewByteRead_ip) I2cWbDat_ob8 <= #1 MasterByteOut_ib8;
+            AppSfp1I2cAccReqMask      <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_App1I2cWrite     : begin
+            if (State_q!=State_d)    I2cSlaveWrReq_oq <= #1 1'b1; 
+            else if (I2cSlaveWrOn_i) I2cSlaveWrReq_oq <= #1 1'b0; 
+            I2cSlaveByte_oqb8         <= #1 I2cWbDat_ib8;            
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b00; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            AppSfp1I2cAccReqMask      <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_App2I2cRead      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b01; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            if (MasterNewByteRead_ip) I2cWbDat_ob8 <= #1 MasterByteOut_ib8;
+            AppSfp2I2cAccReqMask      <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_App2I2cWrite     : begin
+            if (State_q!=State_d)    I2cSlaveWrReq_oq <= #1 1'b1; 
+            else if (I2cSlaveWrOn_i) I2cSlaveWrReq_oq <= #1 1'b0; 
+            I2cSlaveByte_oqb8         <= #1 I2cWbDat_ib8;            
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b01; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            AppSfp2I2cAccReqMask      <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end  
+        s_App3I2cRead      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b10; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            if (MasterNewByteRead_ip) I2cWbDat_ob8 <= #1 MasterByteOut_ib8; 
+            AppSfp3I2cAccReqMask      <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_App3I2cWrite     : begin
+            if (State_q!=State_d)    I2cSlaveWrReq_oq <= #1 1'b1; 
+            else if (I2cSlaveWrOn_i) I2cSlaveWrReq_oq <= #1 1'b0; 
+            I2cSlaveByte_oqb8         <= #1 I2cWbDat_ib8;            
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b10; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            AppSfp3I2cAccReqMask      <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end  
+         s_App4I2cRead      : begin
+            if (State_q!=State_d)    I2cSlaveRdReq_oq <= #1 1'b1; 
+            else if (I2cSlaveRdOn_i) I2cSlaveRdReq_oq <= #1 1'b0; 
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b11; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            if (MasterNewByteRead_ip)  I2cWbDat_ob8 <= #1 MasterByteOut_ib8;
+            AppSfp4I2cAccReqMask      <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        s_App4I2cWrite     : begin
+            if (State_q!=State_d)    I2cSlaveWrReq_oq <= #1 1'b1; 
+            else if (I2cSlaveWrOn_i) I2cSlaveWrReq_oq <= #1 1'b0; 
+            I2cSlaveByte_oqb8         <= #1 I2cWbDat_ib8;            
+            I2cMuxAddress_oq          <= #1 1'b0;
+            I2cMuxChannel_oqb2        <= #1 2'b11; 
+            I2cSlaveAddr_oqb7         <= #1 {6'b101000, I2cWbAdr_ib12[8]};
+            I2cSlaveRegAddr_oqb8      <= #1 I2cWbAdr_ib12[7:0];
+            AppSfp4I2cAccReqMask      <= #1 1'b1;
+            if (MasterTrnDone_p)      I2cWbAck_o   <= #1 1'b1;
+        end 
+        default           : begin
+            InitDone_oq                <= #1 1'b0;
+            IoExpWrReq_oq              <= #1 1'b0;    
+            IoExpRdReq_oq              <= #1 1'b0;     
+            IoExpAddr_oqb3             <= #1 3'b0;
+            IoExpRegAddr_oqb2          <= #1 2'b0; 
+            IoExpData_oqb8             <= #1 8'b0;  
+            I2cSlaveWrReq_oq           <= #1 1'b0;
+            I2cSlaveRdReq_oq           <= #1 1'b0;
+            I2cMuxAddress_oq           <= #1 1'b0;
+            I2cMuxChannel_oqb2         <= #1 2'b0; 
+            I2cSlaveAddr_oqb7          <= #1 7'b0;
+            I2cSlaveRegAddr_oqb8       <= #1 8'b0;
+            I2cSlaveByte_oqb8          <= #1 8'b0;      
+            VmeGa_onqb5                <= #1 5'b0;
+            VmeGaP_onq                 <= #1 1'b0;
+            StatusLed_ob8              <= #1 8'b0;
+            StatusGpIo1A2B_oq          <= #1 1'b0;
+            StatusEnGpIo1Term_oq       <= #1 1'b0;
+            StatusGpIo2A2B_oq          <= #1 1'b0;
+            StatusEnGpIo2Term_oq       <= #1 1'b0;    
+            StatusGpIo34A2B_oq         <= #1 1'b0;
+            StatusEnGpIo3Term_oq       <= #1 1'b0;    
+            StatusEnGpIo4Term_oq       <= #1 1'b0; 
+            BlmIn_oqb8                 <= #1 8'b0;
+            AppSfp1Present_oq          <= #1 1'b0;
+            AppSfp1Id_oq16             <= #1 16'b0;
+            AppSfp1TxFault_oq          <= #1 1'b0;
+            AppSfp1Los_oq              <= #1 1'b0;
+            StatusAppSfp1TxDisable_oq  <= #1 1'b0;
+            StatusAppSfp1RateSelect_oq <= #1 1'b0;    
+            AppSfp2Present_oq          <= #1 1'b0;
+            AppSfp2Id_oq16             <= #1 16'b0;
+            AppSfp2TxFault_oq          <= #1 1'b0;
+            AppSfp2Los_oq              <= #1 1'b0;
+            StatusAppSfp2TxDisable_oq  <= #1 1'b0;
+            StatusAppSfp2RateSelect_oq <= #1 1'b0;    
+            AppSfp3Present_oq          <= #1 1'b0;
+            AppSfp3Id_oq16             <= #1 16'b0;
+            AppSfp3TxFault_oq          <= #1 1'b0;
+            AppSfp3Los_oq              <= #1 1'b0;
+            StatusAppSfp3TxDisable_oq  <= #1 1'b0;
+            StatusAppSfp3RateSelect_oq <= #1 1'b0; 
+            AppSfp4Present_oq          <= #1 1'b0;
+            AppSfp4Id_oq16             <= #1 16'b0;
+            AppSfp4TxFault_oq          <= #1 1'b0;
+            AppSfp4Los_oq              <= #1 1'b0;
+            StatusAppSfp4TxDisable_oq  <= #1 1'b0;
+            StatusAppSfp4RateSelect_oq <= #1 1'b0; 
+            BstSfpPresent_oq           <= #1 1'b0;
+            BstSfpId_oq16              <= #1 16'b0;
+            BstSfpTxFault_oq           <= #1 1'b0;
+            BstSfpLos_oq               <= #1 1'b0;
+            StatusBstSfpTxDisable_oq   <= #1 1'b0;
+            StatusBstSfpRateSelect_oq  <= #1 1'b0;    
+            EthSfpPresent_oq           <= #1 1'b0;
+            EthSfpId_oq16              <= #1 16'b0;
+            EthSfpTxFault_oq           <= #1 1'b0;
+            EthSfpLos_oq               <= #1 1'b0;
+            StatusEthSfpTxDisable_oq   <= #1 1'b0;
+            StatusEthSfpRateSelect_oq  <= #1 1'b0;     
+            CdrLos_oq                  <= #1 1'b0;
+            CdrLol_oq                  <= #1 1'b1;
+            BlmInRdReqMask             <= #1 1'b0;
+            AppSfp12ExpRdReqMask       <= #1 1'b0;
+            AppSfp34ExpRdReqMask       <= #1 1'b0;
+            BstEthSfpExpRdReqMask      <= #1 1'b0;
+            LosExRdReqMask             <= #1 1'b0;
+            AppSfp12ExpWrReqMask       <= #1 1'b0;
+            AppSfp34ExpWrReqMask       <= #1 1'b0;
+            BstEthSfpExpWrReqMask      <= #1 1'b0;
+            GpioExpWrReqMask           <= #1 1'b0;
+            LedExpWrReqMask            <= #1 1'b0;
+            AppSfp1I2cAccReqMask       <= #1 1'b0;
+            AppSfp2I2cAccReqMask       <= #1 1'b0;
+            AppSfp3I2cAccReqMask       <= #1 1'b0;
+            AppSfp4I2cAccReqMask       <= #1 1'b0;
+            BstSfpI2cAccReqMask        <= #1 1'b0;
+            EthSfpI2cAccReqMask        <= #1 1'b0;
+            CdrI2cAccReqMask           <= #1 1'b0;
+            Si57xI2cAccReqMask         <= #1 1'b0;
+            BlmInMuteOthersCnt_c24     <= #1 24'h0;
+            PreAppSfp1Present_q        <= #1 1'b0; 
+            PreAppSfp2Present_q        <= #1 1'b0; 
+            PreAppSfp3Present_q        <= #1 1'b0; 
+            PreAppSfp4Present_q        <= #1 1'b0; 
+            PreEthSfpPresent_q         <= #1 1'b0; 
+            PreBstSfpPresent_q         <= #1 1'b0;  
+            I2cWbAck_o                 <= #1 1'b0;
+        end
+        endcase
+    end
+end
+
+endmodule
--- a/top/vfchd_ref_design/vfchd_i2cmux/README
+++ b/top/vfchd_ref_design/vfchd_i2cmux/README
+All files copied from VFC-HD_System repository of CERN BE-BI[*].
+
+Commit used = fbd74d93f99b54e2ce0dd8d4ae7ff2769234e2d8
+
+[*]: https://gitlab.cern.ch/bi/VFC-HD_System
--- a/top/vfchd_ref_design/vfchd_i2cmux/SfpIdReader.v
+++ b/top/vfchd_ref_design/vfchd_i2cmux/SfpIdReader.v
+`timescale 1ns/1ns
+
+module SfpIdReader #(
+    parameter g_SfpWbBaseAddress = 0,
+	      g_WbAddrWidth = 32)
+(
+    input                            Clk_ik,
+    input                            SfpPlugged_i,
+    output reg                       SfpIdValid_o,
+    output reg             [127 : 0] SfpPN_b128,
+    output reg                       WbCyc_o,
+    output reg                       WbStb_o,
+    output reg [g_WbAddrWidth-1 : 0] WbAddr_ob,
+    input                    [7 : 0] WbData_ib8,
+    input                            WbAck_i);
+
+localparam s_NoSfp    = 0,
+	     s_WbStart  = 1,
+	     s_WbClose  = 2,
+	     s_Done     = 3;
+
+reg [1:0] State_q    = s_NoSfp,
+	     NextState_a;
+
+reg [3:0] ByteRead_c4;
+
+always @(posedge Clk_ik) State_q <= NextState_a;
+
+always @*
+    if (!SfpPlugged_i) NextState_a = s_NoSfp;
+    else begin
+	NextState_a = State_q;
+	case (State_q)
+	    s_NoSfp:    if (SfpPlugged_i) NextState_a = s_WbStart;
+	    s_WbStart:  if (WbAck_i)      NextState_a = s_WbClose;
+	    s_WbClose:  if (!WbAck_i)     NextState_a = &ByteRead_c4 ? s_Done : s_WbStart;
+	    s_Done:;
+	    default: NextState_a = s_NoSfp;
+	endcase
+    end
+
+always @(posedge Clk_ik)
+    case (State_q)
+	s_NoSfp: begin
+	    SfpIdValid_o  <= 1'b0;
+	    ByteRead_c4 <= 4'd0;
+	    WbCyc_o     <= 1'b0;
+	    WbStb_o     <= 1'b0;
+	    WbAddr_ob   <= g_SfpWbBaseAddress + 40;
+	    SfpPN_b128  <= 128'd0;
+	end
+	s_WbStart: begin
+	    WbCyc_o     <= 1'b1;
+	    WbStb_o     <= 1'b1;
+	    if (NextState_a==s_WbClose) SfpPN_b128 <= {SfpPN_b128[119:0], WbData_ib8};
+	end
+	s_WbClose: begin
+	    WbCyc_o     <= 1'b1;
+	    WbStb_o     <= 1'b0;
+	    if (NextState_a==s_WbStart) begin
+		WbAddr_ob   <= WbAddr_ob   + 1'b1;
+		ByteRead_c4 <= ByteRead_c4 + 1'b1;
+	    end
+	end
+	s_Done: begin
+	    SfpIdValid_o  <= 1'b1;
+	    WbCyc_o     <= 1'b0;
+	    WbStb_o     <= 1'b0;
+	end
+    endcase
+
+endmodule
--- a/top/vfchd_ref_design/vfchd_i2cmux/vfchd_i2cmux_pkg.vhd
+++ b/top/vfchd_ref_design/vfchd_i2cmux/vfchd_i2cmux_pkg.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+
+package vfchd_i2cmux_pkg is
+
+  component SfpIdReader is
+    generic (
+      g_SfpWbBaseAddress : natural := 0;
+      g_WbAddrWidth      : natural := 32);
+    port (
+      Clk_ik       : in  std_logic;
+      SfpPlugged_i : in  std_logic;
+      SfpIdValid_o : out std_logic;
+      SfpPN_b128   : out std_logic_vector(127 downto 0);
+      WbCyc_o      : out std_logic;
+      WbStb_o      : out std_logic;
+      WbAddr_ob    : out std_logic_vector(g_WbAddrWidth-1 downto 0);
+      WbData_ib8   : in  std_logic_vector(7 downto 0);
+      WbAck_i      : in  std_logic);
+  end component SfpIdReader;
+
+  component I2cExpAndMuxMaster is
+    generic (
+      g_SclHalfPeriod : std_logic_vector(9 downto 0) := "0100000000");
+    port (
+      Clk_ik              : in    std_logic;
+      Rst_irq             : in    std_logic;
+      IoExpWrReq_i        : in    std_logic;
+      IoExpWrOn_oq        : out   std_logic;
+      IoExpRdReq_i        : in    std_logic;
+      IoExpRdOn_oq        : out   std_logic;
+      IoExpAddr_ib3       : in    std_logic_vector(2 downto 0);
+      IoExpRegAddr_ib2    : in    std_logic_vector(1 downto 0);
+      IoExpData_ib8       : in    std_logic_vector(7 downto 0);
+      I2cSlaveWrReq_i     : in    std_logic;
+      I2cSlaveWrOn_o      : out   std_logic;
+      I2cSlaveRdReq_i     : in    std_logic;
+      I2cSlaveRdOn_o      : out   std_logic;
+      I2cMuxAddress_i     : in    std_logic;
+      I2cMuxChannel_ib2   : in    std_logic_vector(1 downto 0);
+      I2cSlaveAddr_ib7    : in    std_logic_vector(6 downto 0);
+      I2cSlaveRegAddr_ib8 : in    std_logic_vector(7 downto 0);
+      I2cSlaveByte_ib8    : in    std_logic_vector(7 downto 0);
+      Busy_o              : out   std_logic;
+      NewByteRead_op      : out   std_logic;
+      ByteOut_ob8         : out   std_logic_vector(7 downto 0);
+      AckError_op         : out   std_logic;
+      Scl_ioz             : inout std_logic;
+      Sda_ioz             : inout std_logic);
+  end component I2cExpAndMuxMaster;
+
+  component I2cExpAndMuxReqArbiter is
+    port (
+      Clk_ik                     : in  std_logic;
+      Rst_irq                    : in  std_logic;
+      IoExpWrReq_oq              : out std_logic;
+      IoExpWrOn_i                : in  std_logic;
+      IoExpRdReq_oq              : out std_logic;
+      IoExpRdOn_i                : in  std_logic;
+      IoExpAddr_oqb3             : out std_logic_vector(2 downto 0);
+      IoExpRegAddr_oqb2          : out std_logic_vector(1 downto 0);
+      IoExpData_oqb8             : out std_logic_vector(7 downto 0);
+      I2cSlaveWrReq_oq           : out std_logic;
+      I2cSlaveWrOn_i             : in  std_logic;
+      I2cSlaveRdReq_oq           : out std_logic;
+      I2cSlaveRdOn_i             : in  std_logic;
+      I2cMuxAddress_oq           : out std_logic;
+      I2cMuxChannel_oqb2         : out std_logic_vector(1 downto 0);
+      I2cSlaveAddr_oqb7          : out std_logic_vector(6 downto 0);
+      I2cSlaveRegAddr_oqb8       : out std_logic_vector(7 downto 0);
+      I2cSlaveByte_oqb8          : out std_logic_vector(7 downto 0);
+      MasterBusy_i               : in  std_logic;
+      MasterNewByteRead_ip       : in  std_logic;
+      MasterByteOut_ib8          : in  std_logic_vector(7 downto 0);
+      MasterAckError_i           : in  std_logic;
+      IoExpApp12Int_ian          : in  std_logic;
+      IoExpApp34Int_ian          : in  std_logic;
+      IoExpBstEthInt_ian         : in  std_logic;
+      IoExpLosInt_ian            : in  std_logic;
+      IoExpBlmInInt_ian          : in  std_logic;
+      InitDone_oq                : out std_logic;
+      VmeGa_onqb5                : out std_logic_vector(4 downto 0);
+      VmeGaP_onq                 : out std_logic;
+      Led_ib8                    : in  std_logic_vector(7 downto 0);
+      StatusLed_ob8              : out std_logic_vector(7 downto 0);
+      GpIo1A2B_i                 : in  std_logic;
+      EnGpIo1Term_i              : in  std_logic;
+      GpIo2A2B_i                 : in  std_logic;
+      EnGpIo2Term_i              : in  std_logic;
+      GpIo34A2B_i                : in  std_logic;
+      EnGpIo3Term_i              : in  std_logic;
+      EnGpIo4Term_i              : in  std_logic;
+      StatusGpIo1A2B_oq          : out std_logic;
+      StatusEnGpIo1Term_oq       : out std_logic;
+      StatusGpIo2A2B_oq          : out std_logic;
+      StatusEnGpIo2Term_oq       : out std_logic;
+      StatusGpIo34A2B_oq         : out std_logic;
+      StatusEnGpIo3Term_oq       : out std_logic;
+      StatusEnGpIo4Term_oq       : out std_logic;
+      BlmIn_oqb8                 : out std_logic_vector(7 downto 0);
+      AppSfp1Present_oq          : out std_logic;
+      AppSfp1Id_oq16             : out std_logic_vector(15 downto 0);
+      AppSfp1TxFault_oq          : out std_logic;
+      AppSfp1Los_oq              : out std_logic;
+      AppSfp1TxDisable_i         : in  std_logic;
+      AppSfp1RateSelect_i        : in  std_logic;
+      StatusAppSfp1TxDisable_oq  : out std_logic;
+      StatusAppSfp1RateSelect_oq : out std_logic;
+      AppSfp2Present_oq          : out std_logic;
+      AppSfp2Id_oq16             : out std_logic_vector(15 downto 0);
+      AppSfp2TxFault_oq          : out std_logic;
+      AppSfp2Los_oq              : out std_logic;
+      AppSfp2TxDisable_i         : in  std_logic;
+      AppSfp2RateSelect_i        : in  std_logic;
+      StatusAppSfp2TxDisable_oq  : out std_logic;
+      StatusAppSfp2RateSelect_oq : out std_logic;
+      AppSfp3Present_oq          : out std_logic;
+      AppSfp3Id_oq16             : out std_logic_vector(15 downto 0);
+      AppSfp3TxFault_oq          : out std_logic;
+      AppSfp3Los_oq              : out std_logic;
+      AppSfp3TxDisable_i         : in  std_logic;
+      AppSfp3RateSelect_i        : in  std_logic;
+      StatusAppSfp3TxDisable_oq  : out std_logic;
+      StatusAppSfp3RateSelect_oq : out std_logic;
+      AppSfp4Present_oq          : out std_logic;
+      AppSfp4Id_oq16             : out std_logic_vector(15 downto 0);
+      AppSfp4TxFault_oq          : out std_logic;
+      AppSfp4Los_oq              : out std_logic;
+      AppSfp4TxDisable_i         : in  std_logic;
+      AppSfp4RateSelect_i        : in  std_logic;
+      StatusAppSfp4TxDisable_oq  : out std_logic;
+      StatusAppSfp4RateSelect_oq : out std_logic;
+      BstSfpPresent_oq           : out std_logic;
+      BstSfpId_oq16              : out std_logic_vector(15 downto 0);
+      BstSfpTxFault_oq           : out std_logic;
+      BstSfpLos_oq               : out std_logic;
+      BstSfpTxDisable_i          : in  std_logic;
+      BstSfpRateSelect_i         : in  std_logic;
+      StatusBstSfpTxDisable_oq   : out std_logic;
+      StatusBstSfpRateSelect_oq  : out std_logic;
+      EthSfpPresent_oq           : out std_logic;
+      EthSfpId_oq16              : out std_logic_vector(15 downto 0);
+      EthSfpTxFault_oq           : out std_logic;
+      EthSfpLos_oq               : out std_logic;
+      EthSfpTxDisable_i          : in  std_logic;
+      EthSfpRateSelect_i         : in  std_logic;
+      StatusEthSfpTxDisable_oq   : out std_logic;
+      StatusEthSfpRateSelect_oq  : out std_logic;
+      CdrLos_oq                  : out std_logic;
+      CdrLol_oq                  : out std_logic;
+      I2cWbCyc_i                 : in  std_logic;
+      I2cWbStb_i                 : in  std_logic;
+      I2cWbWe_i                  : in  std_logic;
+      I2cWbAdr_ib12              : in  std_logic_vector(11 downto 0);
+      I2cWbDat_ib8               : in  std_logic_vector(7 downto 0);
+      I2cWbDat_ob8               : out std_logic_vector(7 downto 0);
+      I2cWbAck_o                 : out std_logic;
+      WbCyc_i                    : in  std_logic;
+      WbStb_i                    : in  std_logic;
+      WbWe_i                     : in  std_logic;
+      WbDat_ib32                 : in  std_logic_vector(31 downto 0);
+      WbDat_oqb32                : out std_logic_vector(31 downto 0);
+      WbAck_oa                   : out std_logic);
+  end component I2cExpAndMuxReqArbiter;
+
+end vfchd_i2cmux_pkg;
--- a/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
+++ b/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC reference design for VFC-HD
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : vfchd_wr_ref_top.vhd
+-- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2017-01-24
+-- Last update: 2017-02-17
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level file for the WRPC reference design on the VFC-HD.
+--
+-- This is a reference top HDL that instanciates the WR PTP Core together with
+-- its peripherals to be run on a VFC-HD card.
+--
+-- There are two main usecases for this HDL file:
+-- * let new users easily synthesize a WR PTP Core bitstream that can be run on
+--   reference hardware
+-- * provide a reference top HDL file showing how the WRPC can be instantiated
+--   in HDL projects.
+--
+-- VFC-HD:  http://www.ohwr.org/projects/vfc-hd/
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.xvme64x_core_pkg.all;
+use work.wr_vfchd_pkg.all;
+use work.vfchd_i2cmux_pkg.all;
+
+entity vfchd_wr_ref_top is
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- Clock inputs from the board
+    clk_board_125m_i : in std_logic;
+    clk_board_20m_i  : in std_logic;
+
+    -- Reset input (active low, can be async)
+    areset_n_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- VME interface
+    ---------------------------------------------------------------------------
+
+    vme_write_n_i   : in    std_logic;
+    vme_lword_n_b   : inout std_logic;
+    vme_iackout_n_o : out   std_logic;
+    vme_iackin_n_i  : in    std_logic;
+    vme_iack_n_i    : in    std_logic;
+    vme_dtack_oe_o  : out   std_logic;
+    vme_ds_n_i      : in    std_logic_vector(1 downto 0);
+    vme_data_oe_n_o : out   std_logic;
+    vme_data_dir_o  : out   std_logic;
+    vme_as_n_i      : in    std_logic;
+    vme_addr_oe_n_o : out   std_logic;
+    vme_addr_dir_o  : out   std_logic;
+    vme_irq_n_o     : out   std_logic_vector(7 downto 1);
+    vme_data_b      : inout std_logic_vector(31 downto 0);
+    vme_am_i        : in    std_logic_vector(5 downto 0);
+    vme_addr_b      : inout std_logic_vector(31 downto 1);
+
+    ---------------------------------------------------------------------------
+    -- SPI interfaces to DACs
+    ---------------------------------------------------------------------------
+
+    dac_ref_sync_n_o  : out std_logic;
+    dac_dmtd_sync_n_o : out std_logic;
+    dac_din_o         : out std_logic;
+    dac_sclk_o        : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SPI interfaces to VFC Vadj and VADC
+    ---------------------------------------------------------------------------
+
+    --vfc_vadj_cs_n_o : out std_logic;
+    --vfc_vadj_din_o  : out std_logic;
+    --vfc_vadj_sck_o  : out std_logic;
+
+    --vfc_vadc_cs_n_o : out std_logic;
+    --vfc_vadc_din_o  : out std_logic;
+    --vfc_vadc_dout_i : in  std_logic;
+    --vfc_vadc_sck_o  : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver
+    ---------------------------------------------------------------------------
+
+    sfp_tx_o : out std_logic;
+    sfp_rx_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- VFC IO/I2C Mux
+    ---------------------------------------------------------------------------
+
+    i2c_mux_sda_b : inout std_logic;
+    i2c_mux_scl_b : inout std_logic;
+
+    io_exp_irq_bsteth_n_i : in std_logic;
+    io_exp_irq_los_n_i    : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- I2C EEPROM
+    ---------------------------------------------------------------------------
+
+    eeprom_sda_b : inout std_logic;
+    eeprom_scl_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+
+    onewire_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- FMC DIO mezzannine and VFC GPIOs
+    ---------------------------------------------------------------------------
+
+    fmc_enable_n_o : out std_logic;
+    dio_led_term_o : out std_logic;
+    dio_led_out_o  : out std_logic;
+    dio1_i         : in  std_logic;   -- LEMO1 as input for ext PPS in
+    dio1_oe_n_o    : out std_logic;   -- LEMO1 output enable control
+    dio1_term_en_o : out std_logic;   -- LEMO1 output termination control
+    dio5_clk_i     : in  std_logic;   -- LEMO5 clock input for ext 10MHz
+    dio5_oe_n_o    : out std_logic;   -- LEMO5 output enable control
+    dio5_term_en_o : out std_logic;   -- LEMO5 output termination control
+    vfchd_gpio3_o  : out std_logic;   -- VFC GPIO3 for PPS ref output
+    vfchd_gpio4_o  : out std_logic);  -- VFC GPIO4 for ref clock output
+
+end entity vfchd_wr_ref_top;
+
+architecture top of vfchd_wr_ref_top is
+
+  -----------------------------------------------------------------------------
+  -- Constants
+  -----------------------------------------------------------------------------
+
+  -- Number of masters on the primary wishbone crossbar
+  constant c_NUM_WB1_MASTERS : integer := 2;
+
+  -- Number of slaves on the primary wishbone crossbar
+  constant c_NUM_WB1_SLAVES : integer := 3;
+
+  -- Number of masters on the secondary wishbone crossbar
+  constant c_NUM_WB2_MASTERS : integer := 2;
+
+  -- Number of slaves on the secondary wishbone crossbar
+  constant c_NUM_WB2_SLAVES : integer := 1;
+
+  -- Primary Wishbone master(s) offsets
+  constant c_WB_MASTER_VME     : integer := 0;
+  constant c_WB_MASTER_ETHBONE : integer := 1;
+
+  -- Primary Wishbone slave(s) offsets
+  constant c_WB_SLAVE_I2CCFG : integer := 0;
+  constant c_WB_SLAVE_SECOND : integer := 1;
+  constant c_WB_SLAVE_WRC    : integer := 2;
+
+  -- Secondary Wishbone master(s) offsets
+  constant c_WB_MASTER_PRIM  : integer := 0;
+  constant c_WB_MASTER_SFPID : integer := 1;
+
+  -- Secondary Wishbone slave(s) offsets
+  constant c_WB_SLAVE_I2CMUX : integer := 0;
+
+  -- sdb header address on primary crossbar
+  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
+
+  -- SDB record for IO Exp configuration port
+  constant c_xwb_i2ccfg_sdb : t_sdb_device := (
+    abi_class     => x"0000",                     -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"1",                        -- 8-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"0000000000000003",
+      product     => (
+        vendor_id => x"000000000000CE42",         -- CERN
+        device_id => x"00008889",
+        version   => x"00000001",
+        date      => x"20170126",
+        name      => "BE-BI I2C Mux Cfg  ")));
+
+  constant c_mux_bridge_sdb : t_sdb_bridge :=
+    f_xwb_bridge_manual_sdb(x"00003fff", x"00000000");
+
+  -- f_xwb_bridge_manual_sdb(size, sdb_addr)
+  -- Note: sdb_addr is the sdb records address relative to the bridge base address
+  constant c_wrc_bridge_sdb : t_sdb_bridge :=
+    f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
+
+  -- Primary wishbone crossbar layout
+  constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB1_SLAVES - 1 downto 0) := (
+    c_WB_SLAVE_I2CCFG => f_sdb_embed_device(c_xwb_i2ccfg_sdb, x"00001000"),
+    c_WB_SLAVE_SECOND => f_sdb_embed_bridge(c_mux_bridge_sdb, x"00004000"),
+    c_WB_SLAVE_WRC    => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000"));
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- Wishbone buse(s) from masters attached to primary crossbar
+  signal cnx1_master_out : t_wishbone_master_out_array(c_NUM_WB1_MASTERS-1 downto 0);
+  signal cnx1_master_in  : t_wishbone_master_in_array(c_NUM_WB1_MASTERS-1 downto 0);
+
+  -- Wishbone buse(s) to slaves attached to primary crossbar
+  signal cnx1_slave_out : t_wishbone_slave_out_array(c_NUM_WB1_SLAVES-1 downto 0);
+  signal cnx1_slave_in  : t_wishbone_slave_in_array(c_NUM_WB1_SLAVES-1 downto 0);
+
+  -- Wishbone buse(s) from masters attached to secondary crossbar
+  signal cnx2_master_out : t_wishbone_master_out_array(c_NUM_WB2_MASTERS-1 downto 0);
+  signal cnx2_master_in  : t_wishbone_master_in_array(c_NUM_WB2_MASTERS-1 downto 0);
+
+  -- Wishbone buse(s) to slaves attached to secondary crossbar
+  signal cnx2_slave_out : t_wishbone_slave_out_array(c_NUM_WB2_SLAVES-1 downto 0);
+  signal cnx2_slave_in  : t_wishbone_slave_in_array(c_NUM_WB2_SLAVES-1 downto 0);
+
+  -- clock and reset
+  signal clk_sys_62m5 : std_logic;
+  signal rst_sys_62m5 : std_logic;
+  signal clk_ref_125m : std_logic;
+  signal clk_ref_div2 : std_logic;
+
+  -- I2C EEPROM
+  signal eeprom_sda_in  : std_logic;
+  signal eeprom_sda_out : std_logic;
+  signal eeprom_scl_in  : std_logic;
+  signal eeprom_scl_out : std_logic;
+
+  -- VME
+  signal vme_data_b_out    : std_logic_vector(31 downto 0);
+  signal vme_addr_b_out    : std_logic_vector(31 downto 1);
+  signal vme_lword_n_b_out : std_logic;
+  signal Vme_data_dir_int  : std_logic;
+  signal vme_addr_dir_int  : std_logic;
+  signal vme_dtack_n       : std_logic;
+  signal vme_ga            : std_logic_vector(5 downto 0);
+
+  -- SFP
+  signal sfp_det_valid  : std_logic;
+  signal sfp_data       : std_logic_vector (127 downto 0);
+  signal sfp_wb_adr     : t_wishbone_address;
+  signal sfp_tx_fault   : std_logic;
+  signal sfp_los        : std_logic;
+  signal sfp_tx_disable : std_logic;
+
+  -- OneWire
+  signal onewire_data : std_logic;
+  signal onewire_oe   : std_logic;
+
+  -- IO/I2C Mux
+  signal io_exp_init_done : std_logic;
+  signal io_exp_wr_req    : std_logic;
+  signal io_exp_wr_on     : std_logic;
+  signal io_exp_rd_req    : std_logic;
+  signal io_exp_rd_on     : std_logic;
+  signal io_exp_addr      : std_logic_vector(2 downto 0);
+  signal io_exp_reg_addr  : std_logic_vector(1 downto 0);
+  signal io_exp_data      : std_logic_vector(7 downto 0);
+  signal i2c_slv_wr_req   : std_logic;
+  signal i2c_slv_wr_on    : std_logic;
+  signal i2c_slv_rd_req   : std_logic;
+  signal i2c_slv_rd_on    : std_logic;
+  signal i2c_slv_addr     : std_logic_vector(6 downto 0);
+  signal i2c_slv_reg_addr : std_logic_vector(7 downto 0);
+  signal i2c_slv_byte     : std_logic_vector(7 downto 0);
+  signal i2c_mux_addr     : std_logic;
+  signal i2c_mux_channel  : std_logic_vector(1 downto 0);
+  signal i2c_mst_busy     : std_logic;
+  signal i2c_mst_dav      : std_logic;
+  signal i2c_mst_ack_err  : std_logic;
+  signal i2c_mst_data     : std_logic_vector(7 downto 0);
+  signal i2c_wb_adr       : std_logic_vector(11 downto 0);
+  signal i2c_wb_dat_in    : std_logic_vector(7 downto 0);
+  signal i2c_wb_dat_out   : std_logic_vector(7 downto 0);
+
+  -- LEDs
+  signal pps_led     : std_logic;
+  signal pps_led_d   : std_logic;
+  signal vfchd_led   : std_logic_vector(7 downto 0);
+  signal wr_led_link : std_logic;
+  signal wr_led_act  : std_logic;
+
+begin  -- architecture top
+
+  -----------------------------------------------------------------------------
+  -- Primary wishbone Crossbar
+  -----------------------------------------------------------------------------
+
+  cmp_primary_sdb_crossbar : xwb_sdb_crossbar
+    generic map (
+      g_num_masters => c_NUM_WB1_MASTERS,
+      g_num_slaves  => c_NUM_WB1_SLAVES,
+      g_registered  => TRUE,
+      g_wraparound  => TRUE,
+      g_layout      => c_WB_LAYOUT,
+      g_sdb_addr    => c_SDB_ADDRESS)
+    port map (
+      clk_sys_i => clk_sys_62m5,
+      rst_n_i   => not rst_sys_62m5,
+      slave_i   => cnx1_master_out,
+      slave_o   => cnx1_master_in,
+      master_i  => cnx1_slave_out,
+      master_o  => cnx1_slave_in);
+
+  -----------------------------------------------------------------------------
+  -- VME64x Core (WB Master #1)
+  -----------------------------------------------------------------------------
+
+  cmp_vme_core : xvme64x_core
+    port map (
+      clk_i           => clk_sys_62m5,
+      rst_n_i         => not rst_sys_62m5,
+      VME_AS_n_i      => vme_as_n_i,
+      VME_RST_n_i     => io_exp_init_done,
+      VME_WRITE_n_i   => vme_write_n_i,
+      VME_AM_i        => vme_am_i,
+      VME_DS_n_i      => vme_ds_n_i,
+      VME_GA_i        => vme_ga,
+      VME_BERR_o      => open,
+      VME_DTACK_n_o   => vme_dtack_n,
+      VME_RETRY_n_o   => open,
+      VME_RETRY_OE_o  => open,
+      VME_LWORD_n_b_i => vme_lword_n_b,
+      VME_LWORD_n_b_o => vme_lword_n_b_out,
+      VME_ADDR_b_i    => vme_addr_b,
+      VME_DATA_b_o    => vme_data_b_out,
+      VME_ADDR_b_o    => vme_addr_b_out,
+      VME_DATA_b_i    => vme_data_b,
+      VME_IRQ_n_o     => vme_irq_n_o,
+      VME_IACK_n_i    => vme_iack_n_i,
+      VME_IACKIN_n_i  => vme_iackin_n_i,
+      VME_IACKOUT_n_o => vme_iackout_n_o,
+      VME_DTACK_OE_o  => open,
+      VME_DATA_DIR_o  => vme_data_dir_int,
+      VME_DATA_OE_N_o => vme_data_oe_n_o,
+      VME_ADDR_DIR_o  => vme_addr_dir_int,
+      VME_ADDR_OE_N_o => vme_addr_oe_n_o,
+      master_o        => cnx1_master_out(c_WB_MASTER_VME),
+      master_i        => cnx1_master_in(c_WB_MASTER_VME),
+      irq_i           => '0');
+
+  -- Handle DTACK according to VFC-HD hardware
+  vme_dtack_oe_o <= not vme_dtack_n;
+
+  -- VME tri-state buffers
+  vme_data_b    <= vme_data_b_out    when vme_data_dir_int = '1' else (others => 'Z');
+  vme_addr_b    <= vme_addr_b_out    when vme_addr_dir_int = '1' else (others => 'Z');
+  vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
+
+  vme_addr_dir_o <= vme_addr_dir_int;
+  vme_data_dir_o <= vme_data_dir_int;
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
+  -----------------------------------------------------------------------------
+
+  cmp_xwrc_board_vfchd : xwrc_board_vfchd
+    generic map (
+      g_with_external_clock_input => TRUE,
+      g_fabric_iface              => "etherbone")
+    port map (
+      clk_board_125m_i  => clk_board_125m_i,
+      clk_board_20m_i   => clk_board_20m_i,
+      clk_ext_10m_i     => dio5_clk_i,
+      areset_n_i        => areset_n_i,
+      clk_sys_62m5_o    => clk_sys_62m5,
+      clk_ref_125m_o    => clk_ref_125m,
+      rst_sys_62m5_o    => rst_sys_62m5,
+      dac_ref_sync_n_o  => dac_ref_sync_n_o,
+      dac_dmtd_sync_n_o => dac_dmtd_sync_n_o,
+      dac_din_o         => dac_din_o,
+      dac_sclk_o        => dac_sclk_o,
+      sfp_tx_o          => sfp_tx_o,
+      sfp_rx_i          => sfp_rx_i,
+      sfp_det_valid_i   => sfp_det_valid,
+      sfp_data_i        => sfp_data,
+      sfp_tx_fault_i    => sfp_tx_fault,
+      sfp_los_i         => sfp_los,
+      sfp_tx_disable_o  => sfp_tx_disable,
+      eeprom_sda_i      => eeprom_sda_in,
+      eeprom_sda_o      => eeprom_sda_out,
+      eeprom_scl_i      => eeprom_scl_in,
+      eeprom_scl_o      => eeprom_scl_out,
+      onewire_i         => onewire_data,
+      onewire_oen_o     => onewire_oe,
+      wb_slave_o        => cnx1_slave_out(c_WB_SLAVE_WRC),
+      wb_slave_i        => cnx1_slave_in(c_WB_SLAVE_WRC),
+      wb_eth_master_o   => cnx1_master_out(c_WB_MASTER_ETHBONE),
+      wb_eth_master_i   => cnx1_master_in(c_WB_MASTER_ETHBONE),
+      pps_ext_i         => dio1_i,
+      pps_p_o           => vfchd_gpio3_o,
+      pps_led_o         => pps_led,
+      led_link_o        => wr_led_link,
+      led_act_o         => wr_led_act);
+
+  -- tri-state I2C EEPROM
+  eeprom_sda_b  <= '0' when (eeprom_sda_out = '0') else 'Z';
+  eeprom_sda_in <= eeprom_sda_b;
+
+  eeprom_scl_b  <= '0' when (eeprom_scl_out = '0') else 'Z';
+  eeprom_scl_in <= eeprom_scl_b;
+
+  -- tri-state onewire access
+  onewire_b    <= '0' when (onewire_oe = '1') else 'Z';
+  onewire_data <= onewire_b;
+
+  -----------------------------------------------------------------------------
+  -- VFCHD I2C MUX and Arbiter
+  -- Presents two WB Slave ports, one to primary crossbar, one to secondary
+  -----------------------------------------------------------------------------
+
+  cmp_secondary_crossbar : xwb_crossbar
+    generic map (
+      g_num_masters => c_NUM_WB2_MASTERS,
+      g_num_slaves  => c_NUM_WB2_SLAVES,
+      g_registered  => TRUE,
+      g_address     => (0 => (others => '0')),
+      g_mask        => (0 => (others => '0')))
+    port map (
+      clk_sys_i => clk_sys_62m5,
+      rst_n_i   => not rst_sys_62m5,
+      slave_i   => cnx2_master_out,
+      slave_o   => cnx2_master_in,
+      master_i  => cnx2_slave_out,
+      master_o  => cnx2_slave_in);
+
+  -- link with primary crossbar
+  cnx1_slave_out(c_WB_SLAVE_SECOND) <= cnx2_master_in(c_WB_MASTER_PRIM);
+  cnx2_master_out(c_WB_MASTER_PRIM) <= cnx1_slave_in(c_WB_SLAVE_SECOND);
+
+  cmp_SfpIdReader : SfpIdReader
+    generic map (
+      -- g_SfpWbBaseAddress is 0x1a00.
+      -- X"1000" for crossbar (x"4000" >> 2 because of adapter later on)
+      -- X"0a00" from I2cMuxAndExpReqArbiter
+      g_SfpWbBaseAddress => 6656,
+      g_WbAddrWidth      => c_wishbone_address_width)
+    port map (
+      Clk_ik       => clk_sys_62m5,
+      SfpPlugged_i => not sfp_los,
+      SfpIdValid_o => sfp_det_valid,
+      SfpPN_b128   => sfp_data,
+      WbCyc_o      => cnx2_master_out(c_WB_MASTER_SFPID).cyc,
+      WbStb_o      => cnx2_master_out(c_WB_MASTER_SFPID).stb,
+      WbAddr_ob    => sfp_wb_adr,
+      WbData_ib8   => cnx2_master_in(c_WB_MASTER_SFPID).dat(7 downto 0),
+      WbAck_i      => cnx2_master_in(c_WB_MASTER_SFPID).ack);
+
+  -- address adapter needed to properly access each byte in the I2CMux
+  cnx2_master_out(c_WB_MASTER_SFPID).adr <= sfp_wb_adr (29 downto 0) & "00";
+
+  -- Drive unused signals
+  cnx2_master_out(c_WB_MASTER_SFPID).dat <= (others => '0');
+  cnx2_master_out(c_WB_MASTER_SFPID).sel <= (others => '1');
+  cnx2_master_out(c_WB_MASTER_SFPID).we  <= '0';
+
+  cmp_I2cExpAndMuxReqArbiter : I2cExpAndMuxReqArbiter
+    port map (
+      Clk_ik                     => clk_sys_62m5,
+      Rst_irq                    => rst_sys_62m5,
+      IoExpWrReq_oq              => io_exp_wr_req,
+      IoExpWrOn_i                => io_exp_wr_on,
+      IoExpRdReq_oq              => io_exp_rd_req,
+      IoExpRdOn_i                => io_exp_rd_on,
+      IoExpAddr_oqb3             => io_exp_addr,
+      IoExpRegAddr_oqb2          => io_exp_reg_addr,
+      IoExpData_oqb8             => io_exp_data,
+      I2cSlaveWrReq_oq           => i2c_slv_wr_req,
+      I2cSlaveWrOn_i             => i2c_slv_wr_on,
+      I2cSlaveRdReq_oq           => i2c_slv_rd_req,
+      I2cSlaveRdOn_i             => i2c_slv_rd_on,
+      I2cMuxAddress_oq           => i2c_mux_addr,
+      I2cMuxChannel_oqb2         => i2c_mux_channel,
+      I2cSlaveAddr_oqb7          => i2c_slv_addr,
+      I2cSlaveRegAddr_oqb8       => i2c_slv_reg_addr,
+      I2cSlaveByte_oqb8          => i2c_slv_byte,
+      MasterBusy_i               => i2c_mst_busy,
+      MasterNewByteRead_ip       => i2c_mst_dav,
+      MasterByteOut_ib8          => i2c_mst_data,
+      MasterAckError_i           => i2c_mst_ack_err,
+      IoExpApp12Int_ian          => '1',
+      IoExpApp34Int_ian          => '1',
+      IoExpBstEthInt_ian         => io_exp_irq_bsteth_n_i,
+      IoExpLosInt_ian            => io_exp_irq_los_n_i,
+      IoExpBlmInInt_ian          => '1',
+      InitDone_oq                => io_exp_init_done,
+      VmeGa_onqb5                => vme_ga(4 downto 0),
+      VmeGaP_onq                 => vme_ga(5),
+      Led_ib8                    => vfchd_led,
+      StatusLed_ob8              => open,
+      GpIo1A2B_i                 => '0',
+      EnGpIo1Term_i              => '0',
+      GpIo2A2B_i                 => '0',
+      EnGpIo2Term_i              => '0',
+      GpIo34A2B_i                => '1',
+      EnGpIo3Term_i              => '0',
+      EnGpIo4Term_i              => '0',
+      StatusGpIo1A2B_oq          => open,
+      StatusEnGpIo1Term_oq       => open,
+      StatusGpIo2A2B_oq          => open,
+      StatusEnGpIo2Term_oq       => open,
+      StatusGpIo34A2B_oq         => open,
+      StatusEnGpIo3Term_oq       => open,
+      StatusEnGpIo4Term_oq       => open,
+      BlmIn_oqb8                 => open,
+      AppSfp1Present_oq          => open,
+      AppSfp1Id_oq16             => open,
+      AppSfp1TxFault_oq          => open,
+      AppSfp1Los_oq              => open,
+      AppSfp1TxDisable_i         => '0',
+      AppSfp1RateSelect_i        => '0',
+      StatusAppSfp1TxDisable_oq  => open,
+      StatusAppSfp1RateSelect_oq => open,
+      AppSfp2Present_oq          => open,
+      AppSfp2Id_oq16             => open,
+      AppSfp2TxFault_oq          => open,
+      AppSfp2Los_oq              => open,
+      AppSfp2TxDisable_i         => '0',
+      AppSfp2RateSelect_i        => '0',
+      StatusAppSfp2TxDisable_oq  => open,
+      StatusAppSfp2RateSelect_oq => open,
+      AppSfp3Present_oq          => open,
+      AppSfp3Id_oq16             => open,
+      AppSfp3TxFault_oq          => open,
+      AppSfp3Los_oq              => open,
+      AppSfp3TxDisable_i         => '0',
+      AppSfp3RateSelect_i        => '0',
+      StatusAppSfp3TxDisable_oq  => open,
+      StatusAppSfp3RateSelect_oq => open,
+      AppSfp4Present_oq          => open,
+      AppSfp4Id_oq16             => open,
+      AppSfp4TxFault_oq          => open,
+      AppSfp4Los_oq              => open,
+      AppSfp4TxDisable_i         => '0',
+      AppSfp4RateSelect_i        => '0',
+      StatusAppSfp4TxDisable_oq  => open,
+      StatusAppSfp4RateSelect_oq => open,
+      BstSfpPresent_oq           => open,
+      BstSfpId_oq16              => open,
+      BstSfpTxFault_oq           => open,
+      BstSfpLos_oq               => open,
+      BstSfpTxDisable_i          => '0',
+      BstSfpRateSelect_i         => '0',
+      StatusBstSfpTxDisable_oq   => open,
+      StatusBstSfpRateSelect_oq  => open,
+      EthSfpPresent_oq           => open,
+      EthSfpId_oq16              => open,
+      EthSfpTxFault_oq           => sfp_tx_fault,
+      EthSfpLos_oq               => sfp_los,
+      EthSfpTxDisable_i          => sfp_tx_disable,
+      EthSfpRateSelect_i         => '1',
+      StatusEthSfpTxDisable_oq   => open,         -- TODO
+      StatusEthSfpRateSelect_oq  => open,
+      CdrLos_oq                  => open,
+      CdrLol_oq                  => open,
+      I2cWbCyc_i                 => cnx2_slave_in(c_WB_SLAVE_I2CMUX).cyc,
+      I2cWbStb_i                 => cnx2_slave_in(c_WB_SLAVE_I2CMUX).stb,
+      I2cWbWe_i                  => cnx2_slave_in(c_WB_SLAVE_I2CMUX).we,
+      I2cWbAdr_ib12              => i2c_wb_adr,
+      I2cWbDat_ib8               => i2c_wb_dat_in,
+      I2cWbDat_ob8               => i2c_wb_dat_out,
+      I2cWbAck_o                 => cnx2_slave_out(c_WB_SLAVE_I2CMUX).ack,
+      WbCyc_i                    => cnx1_slave_in(c_WB_SLAVE_I2CCFG).cyc,
+      WbStb_i                    => cnx1_slave_in(c_WB_SLAVE_I2CCFG).stb,
+      WbWe_i                     => cnx1_slave_in(c_WB_SLAVE_I2CCFG).we,
+      WbDat_ib32                 => cnx1_slave_in(c_WB_SLAVE_I2CCFG).dat,
+      WbDat_oqb32                => cnx1_slave_out(c_WB_SLAVE_I2CCFG).dat,
+      WbAck_oa                   => cnx1_slave_out(c_WB_SLAVE_I2CCFG).ack);
+
+  -- Adjust WB interface to VFCHD I2CMux expectations and drive unused signals
+  -- Adr(13 downto 10) are used to select the I2C peripheral in the mux
+  -- Adr(9 downto 2) are the I2C address of that peripheral
+  -- Adr(1 downto 0) are dropped (to allow access to the individual bytes
+  -- since I2CMux only provides an 8-bit output)
+  i2c_wb_adr    <= cnx2_slave_in(c_WB_SLAVE_I2CMUX).adr(13 downto 2);
+  i2c_wb_dat_in <= cnx2_slave_in(c_WB_SLAVE_I2CMUX).dat(7 downto 0);
+
+  cnx2_slave_out(c_WB_SLAVE_I2CMUX).dat   <= X"000000" & i2c_wb_dat_out;
+  cnx2_slave_out(c_WB_SLAVE_I2CMUX).err   <= '0';
+  cnx2_slave_out(c_WB_SLAVE_I2CMUX).rty   <= '0';
+  cnx2_slave_out(c_WB_SLAVE_I2CMUX).int   <= '0';
+  cnx2_slave_out(c_WB_SLAVE_I2CMUX).stall <= not cnx2_slave_out(c_WB_SLAVE_I2CMUX).ack and
+                                             (cnx2_slave_in(c_WB_SLAVE_I2CMUX).stb and
+                                              cnx2_slave_in(c_WB_SLAVE_I2CMUX).cyc);
+
+  cnx1_slave_out(c_WB_SLAVE_I2CCFG).err   <= '0';
+  cnx1_slave_out(c_WB_SLAVE_I2CCFG).rty   <= '0';
+  cnx1_slave_out(c_WB_SLAVE_I2CCFG).int   <= '0';
+  cnx1_slave_out(c_WB_SLAVE_I2CCFG).stall <= not cnx1_slave_out(c_WB_SLAVE_I2CCFG).ack and
+                                             (cnx1_slave_in(c_WB_SLAVE_I2CCFG).stb and
+                                              cnx1_slave_in(c_WB_SLAVE_I2CCFG).cyc);
+
+  cmp_I2cExpAndMuxMaster : I2cExpAndMuxMaster
+    generic map (
+      g_SclHalfPeriod => "0010100000")            -- 10'd160
+    port map (
+      Clk_ik              => clk_sys_62m5,
+      Rst_irq             => rst_sys_62m5,
+      IoExpWrReq_i        => io_exp_wr_req,
+      IoExpWrOn_oq        => io_exp_wr_on,
+      IoExpRdReq_i        => io_exp_rd_req,
+      IoExpRdOn_oq        => io_exp_rd_on,
+      IoExpAddr_ib3       => io_exp_addr,
+      IoExpRegAddr_ib2    => io_exp_reg_addr,
+      IoExpData_ib8       => io_exp_data,
+      I2cSlaveWrReq_i     => i2c_slv_wr_req,
+      I2cSlaveWrOn_o      => i2c_slv_wr_on,
+      I2cSlaveRdReq_i     => i2c_slv_rd_req,
+      I2cSlaveRdOn_o      => i2c_slv_rd_on,
+      I2cMuxAddress_i     => i2c_mux_addr,
+      I2cMuxChannel_ib2   => i2c_mux_channel,
+      I2cSlaveAddr_ib7    => i2c_slv_addr,
+      I2cSlaveRegAddr_ib8 => i2c_slv_reg_addr,
+      I2cSlaveByte_ib8    => i2c_slv_byte,
+      Busy_o              => i2c_mst_busy,
+      NewByteRead_op      => i2c_mst_dav,
+      ByteOut_ob8         => i2c_mst_data,
+      AckError_op         => i2c_mst_ack_err,
+      Scl_ioz             => i2c_mux_scl_b,
+      Sda_ioz             => i2c_mux_sda_b);
+
+  -----------------------------------------------------------------------------
+  -- Remaining DIO, VFC GPIO and LEDs
+  -----------------------------------------------------------------------------
+
+  -- extend pulse for PPS LEDs
+  cmp_gc_extend_pulse1 : gc_extend_pulse
+    generic map (
+      g_width => 5000000)
+    port map (
+      clk_i      => clk_sys_62m5,
+      rst_n_i    => not rst_sys_62m5,
+      pulse_i    => pps_led,
+      extended_o => pps_led_d);
+
+  -- assign LEDs
+  vfchd_led <= (0      => wr_led_link,
+                4      => wr_led_act,
+                others => '0');
+
+  -- Debug: Reference clock to GPIO output
+  process(clk_ref_125m)
+  begin
+    if rising_edge(clk_ref_125m) then
+      clk_ref_div2 <= not clk_ref_div2;
+    end if;
+  end process;
+
+  vfchd_gpio4_o <= clk_ref_div2;
+
+  -- Configure DIO LEMO1 and LEMO5 as inputs
+  dio1_term_en_o <= '0';
+  dio1_oe_n_o    <= '1';
+  dio5_term_en_o <= '0';
+  dio5_oe_n_o    <= '1';
+
+  dio_led_term_o <= '0';
+  dio_led_out_o  <= pps_led_d;
+
+  fmc_enable_n_o <= '0';
+
+end architecture top;