[tb/wrpc] bugfix of main top

- the connection of rx/tx to PHY was wrong, there was (very likely unintentional) a loop between tx and rx of PHY. - since there is the (intentional) loop between sink and source of wrpc, frames sent by WRPC SW (LM32) were looping endlessly.

[tb/wrpc] bugfix of main top
- the connection of rx/tx to PHY was wrong, there was (very likely unintentional) a loop between tx and rx of PHY. - since there is the (intentional) loop between sink and source of wrpc, frames sent by WRPC SW (LM32) were looping endlessly.
47a5d869 · Maciej Lipinski · Grzegorz Daniluk · 8431e79d · 47a5d869
Commit 47a5d869 authored Feb 01, 2017 by Maciej Lipinski Committed by Grzegorz Daniluk Feb 14, 2017
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main.sv testbench/wrc_core/main_tb/main.sv +2 -2

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--- a/testbench/wrc_core/main_tb/main.sv
+++ b/testbench/wrc_core/main_tb/main.sv
@@ -154,8 +154,8 @@ module main;
    .phy_tx_disparity_i         (phy_tx_disparity),
    .phy_tx_enc_err_i           (phy_tx_enc_err),
    .phy_rx_rbclk_i             (clk_ref),
-    .phy_rx_data_i              (phy_tx_data),
-    .phy_rx_k_i                 (phy_tx_k),
+    .phy_rx_data_i              (phy_rx_data),
+    .phy_rx_k_i                 (phy_rx_k),
    .phy_rx_enc_err_i           (phy_rx_enc_err),
    .phy_rx_bitslide_i          (phy_rx_bitslide),
    .phy_rst_o                  (phy_rst),