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White Rabbit core collection
Commit 48db02c0 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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modules/wrc_core: wr ptp core cannot depend from etherbone

parent b3fe4f75
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Showing with 7 additions and 5 deletions
modules/wrc_core/wr_core.vhd
View file @ 48db02c0
......@@ -55,7 +55,6 @@ use work.wishbone_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.etherbone_pkg.all;
entity wr_core is
generic(
......@@ -72,7 +71,7 @@ entity wr_core is
g_dpram_size : integer := 20480; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_etherbone_sdb
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
);
port(
......
modules/wrc_core/xwr_core.vhd
View file @ 48db02c0
......@@ -56,7 +56,8 @@ entity xwr_core is
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_dpram_size : integer := 20480; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
);
port(
---------------------------------------------------------------------------
......@@ -202,7 +203,8 @@ architecture struct of xwr_core is
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_dpram_size : integer := 16384; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
......@@ -333,7 +335,8 @@ begin
g_dpram_initv => g_dpram_initv,
g_dpram_size => g_dpram_size,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity)
g_address_granularity => g_address_granularity,
g_aux_sdb => g_aux_sdb)
port map(
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
......
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