Commit 4e70a456 authored by Maciej Lipinski's avatar Maciej Lipinski

[cute/top] added synchronizer bringing pll_aux_locked to clk_pll_125m clock domain

It seems that pll_aux_locked is in clk_sys clock domain. When
synthesising cute for BTrain I had timing errors in the 10MHz
generation process. This commit fixes the timing issues.
parent 79f5b749
Pipeline #184 failed with stages
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