Commit 4f8ec131 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

sim: fix whitespace error

parent f9d86db3
Pipeline #51 passed with stages
in 11 minutes and 20 seconds
......@@ -316,7 +316,7 @@ module wr_1000basex_phy_model
assign ser_rx = loopen_i ? ser_tx : pad_rxp_i;
assign pad_txp_o = loopen_i == 1'b1 ? 1'bz : ser_tx;
assign pad_txn_o = loopen_i == 1'b1? 1'bz : ~ser_tx;
assign pad_txn_o = loopen_i == 1'b1 ? 1'bz : ~ser_tx;
endmodule // wr_1000basex_phy_model
......
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