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White Rabbit core collection
Commit 52a169e7 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_softpll_ng: make new register layout compatible with the previous version of SoftPLL

parent 120c203d
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modules/wr_softpll_ng/spll_wb_slave.vhd
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...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd -- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb -- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Wed Mar 20 10:53:43 2013 -- Created : Thu Jul 25 11:14:53 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
...@@ -20,936 +20,931 @@ use work.spll_wbgen2_pkg.all; ...@@ -20,936 +20,931 @@ use work.spll_wbgen2_pkg.all;
entity spll_wb_slave is entity spll_wb_slave is
generic ( generic (
g_with_debug_fifo : integer := 1); g_with_debug_fifo : integer := 1 );
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0); wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
wb_int_o : out std_logic; wb_int_o : out std_logic;
irq_tag_i : in std_logic; irq_tag_i : in std_logic;
regs_i : in t_spll_in_registers; regs_i : in t_spll_in_registers;
regs_o : out t_spll_out_registers regs_o : out t_spll_out_registers
); );
end spll_wb_slave; end spll_wb_slave;
architecture syn of spll_wb_slave is architecture syn of spll_wb_slave is
signal spll_eccr_ext_en_int : std_logic; signal spll_eccr_ext_en_int : std_logic ;
signal spll_eccr_align_en_int : std_logic; signal spll_eccr_align_en_int : std_logic ;
signal spll_occr_out_lock_int : std_logic_vector(7 downto 0); signal spll_occr_out_lock_int : std_logic_vector(7 downto 0);
signal spll_deglitch_thr_int : std_logic_vector(15 downto 0); signal spll_deglitch_thr_int : std_logic_vector(15 downto 0);
signal spll_dfr_host_rst_n : std_logic; signal spll_dfr_host_rst_n : std_logic ;
signal spll_dfr_host_in_int : std_logic_vector(47 downto 0); signal spll_dfr_host_in_int : std_logic_vector(47 downto 0);
signal spll_dfr_host_out_int : std_logic_vector(47 downto 0); signal spll_dfr_host_out_int : std_logic_vector(47 downto 0);
signal spll_dfr_host_rdreq_int : std_logic; signal spll_dfr_host_rdreq_int : std_logic ;
signal spll_dfr_host_rdreq_int_d0 : std_logic; signal spll_dfr_host_rdreq_int_d0 : std_logic ;
signal spll_trr_rst_n : std_logic; signal spll_trr_rst_n : std_logic ;
signal spll_trr_in_int : std_logic_vector(31 downto 0); signal spll_trr_in_int : std_logic_vector(31 downto 0);
signal spll_trr_out_int : std_logic_vector(31 downto 0); signal spll_trr_out_int : std_logic_vector(31 downto 0);
signal spll_trr_rdreq_int : std_logic; signal spll_trr_rdreq_int : std_logic ;
signal spll_trr_rdreq_int_d0 : std_logic; signal spll_trr_rdreq_int_d0 : std_logic ;
signal eic_idr_int : std_logic_vector(0 downto 0); signal eic_idr_int : std_logic_vector(0 downto 0);
signal eic_idr_write_int : std_logic; signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(0 downto 0); signal eic_ier_int : std_logic_vector(0 downto 0);
signal eic_ier_write_int : std_logic; signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(0 downto 0); signal eic_imr_int : std_logic_vector(0 downto 0);
signal eic_isr_clear_int : std_logic_vector(0 downto 0); signal eic_isr_clear_int : std_logic_vector(0 downto 0);
signal eic_isr_status_int : std_logic_vector(0 downto 0); signal eic_isr_status_int : std_logic_vector(0 downto 0);
signal eic_irq_ack_int : std_logic_vector(0 downto 0); signal eic_irq_ack_int : std_logic_vector(0 downto 0);
signal eic_isr_write_int : std_logic; signal eic_isr_write_int : std_logic ;
signal spll_dfr_host_full_int : std_logic; signal spll_dfr_host_full_int : std_logic ;
signal spll_dfr_host_empty_int : std_logic; signal spll_dfr_host_empty_int : std_logic ;
signal spll_dfr_host_usedw_int : std_logic_vector(12 downto 0); signal spll_dfr_host_usedw_int : std_logic_vector(12 downto 0);
signal spll_trr_empty_int : std_logic; signal spll_trr_empty_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(0 downto 0); signal irq_inputs_vector_int : std_logic_vector(0 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0); signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0); signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic; signal ack_in_progress : std_logic ;
signal wr_int : std_logic; signal wr_int : std_logic ;
signal rd_int : std_logic; signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0); signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0); signal allzeros : std_logic_vector(31 downto 0);
begin begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards. -- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i; wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i; bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1'); allones <= (others => '1');
allzeros <= (others => '0'); allzeros <= (others => '0');
-- --
-- Main register bank access process. -- Main register bank access process.
process (clk_sys_i, rst_n_i) process (clk_sys_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
ack_sreg <= "0000000000"; ack_sreg <= "0000000000";
ack_in_progress <= '0'; ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
spll_eccr_ext_en_int <= '0'; spll_eccr_ext_en_int <= '0';
spll_eccr_align_en_int <= '0'; spll_eccr_align_en_int <= '0';
spll_occr_out_lock_int <= "00000000"; spll_occr_out_lock_int <= "00000000";
regs_o.rcer_load_o <= '0'; regs_o.rcer_load_o <= '0';
regs_o.ocer_load_o <= '0'; regs_o.ocer_load_o <= '0';
regs_o.dac_hpll_wr_o <= '0'; regs_o.dac_hpll_wr_o <= '0';
regs_o.dac_main_value_wr_o <= '0'; regs_o.dac_main_value_wr_o <= '0';
regs_o.dac_main_dac_sel_wr_o <= '0'; regs_o.dac_main_dac_sel_wr_o <= '0';
spll_deglitch_thr_int <= "0000000000000000"; spll_deglitch_thr_int <= "0000000000000000";
regs_o.dfr_spll_value_wr_o <= '0'; regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0'; regs_o.dfr_spll_eos_wr_o <= '0';
regs_o.crr_in_load_o <= '0'; regs_o.crr_in_load_o <= '0';
regs_o.crr_out_load_o <= '0'; regs_o.crr_out_load_o <= '0';
regs_o.aux_cr_aux_sel_wr_o <= '0'; regs_o.aux_cr_aux_sel_wr_o <= '0';
regs_o.aux_cr_div_ref_wr_o <= '0'; regs_o.aux_cr_div_ref_wr_o <= '0';
regs_o.aux_cr_div_fb_wr_o <= '0'; regs_o.aux_cr_div_fb_wr_o <= '0';
regs_o.aux_cr_gate_wr_o <= '0'; regs_o.aux_cr_gate_wr_o <= '0';
eic_idr_write_int <= '0'; eic_idr_write_int <= '0';
eic_ier_write_int <= '0'; eic_ier_write_int <= '0';
eic_isr_write_int <= '0'; eic_isr_write_int <= '0';
spll_dfr_host_rdreq_int <= '0'; spll_dfr_host_rdreq_int <= '0';
spll_trr_rdreq_int <= '0'; spll_trr_rdreq_int <= '0';
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0'; ack_sreg(9) <= '0';
if (ack_in_progress = '1') then if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then if (ack_sreg(0) = '1') then
regs_o.rcer_load_o <= '0'; regs_o.rcer_load_o <= '0';
regs_o.ocer_load_o <= '0'; regs_o.ocer_load_o <= '0';
regs_o.dac_hpll_wr_o <= '0'; regs_o.dac_hpll_wr_o <= '0';
regs_o.dac_main_value_wr_o <= '0'; regs_o.dac_main_value_wr_o <= '0';
regs_o.dac_main_dac_sel_wr_o <= '0'; regs_o.dac_main_dac_sel_wr_o <= '0';
regs_o.dfr_spll_value_wr_o <= '0'; regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0'; regs_o.dfr_spll_eos_wr_o <= '0';
regs_o.crr_in_load_o <= '0'; regs_o.crr_in_load_o <= '0';
regs_o.crr_out_load_o <= '0'; regs_o.crr_out_load_o <= '0';
regs_o.aux_cr_aux_sel_wr_o <= '0'; regs_o.aux_cr_aux_sel_wr_o <= '0';
regs_o.aux_cr_div_ref_wr_o <= '0'; regs_o.aux_cr_div_ref_wr_o <= '0';
regs_o.aux_cr_div_fb_wr_o <= '0'; regs_o.aux_cr_div_fb_wr_o <= '0';
regs_o.aux_cr_gate_wr_o <= '0'; regs_o.aux_cr_gate_wr_o <= '0';
eic_idr_write_int <= '0'; eic_idr_write_int <= '0';
eic_ier_write_int <= '0'; eic_ier_write_int <= '0';
eic_isr_write_int <= '0'; eic_isr_write_int <= '0';
ack_in_progress <= '0'; ack_in_progress <= '0';
else else
regs_o.rcer_load_o <= '0'; regs_o.rcer_load_o <= '0';
regs_o.ocer_load_o <= '0'; regs_o.ocer_load_o <= '0';
regs_o.dac_hpll_wr_o <= '0'; regs_o.dac_hpll_wr_o <= '0';
regs_o.dac_main_value_wr_o <= '0'; regs_o.dac_main_value_wr_o <= '0';
regs_o.dac_main_dac_sel_wr_o <= '0'; regs_o.dac_main_dac_sel_wr_o <= '0';
regs_o.dfr_spll_value_wr_o <= '0'; regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0'; regs_o.dfr_spll_eos_wr_o <= '0';
regs_o.crr_in_load_o <= '0'; regs_o.crr_in_load_o <= '0';
regs_o.crr_out_load_o <= '0'; regs_o.crr_out_load_o <= '0';
regs_o.aux_cr_aux_sel_wr_o <= '0'; regs_o.aux_cr_aux_sel_wr_o <= '0';
regs_o.aux_cr_div_ref_wr_o <= '0'; regs_o.aux_cr_div_ref_wr_o <= '0';
regs_o.aux_cr_div_fb_wr_o <= '0'; regs_o.aux_cr_div_fb_wr_o <= '0';
regs_o.aux_cr_gate_wr_o <= '0'; regs_o.aux_cr_gate_wr_o <= '0';
end if; end if;
else else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is case rwaddr_reg(4 downto 0) is
when "00000" => when "00000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(5 downto 0) <= regs_i.csr_n_ref_i; rddata_reg(5 downto 0) <= "000000";
rddata_reg(10 downto 8) <= regs_i.csr_n_out_i; rddata_reg(13 downto 8) <= regs_i.csr_n_ref_i;
rddata_reg(11) <= regs_i.csr_dbg_supported_i; rddata_reg(18 downto 16) <= regs_i.csr_n_out_i;
rddata_reg(6) <= 'X'; rddata_reg(19) <= regs_i.csr_dbg_supported_i;
rddata_reg(7) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "00001" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; spll_eccr_ext_en_int <= wrdata_reg(0);
ack_sreg(0) <= '1'; spll_eccr_align_en_int <= wrdata_reg(2);
ack_in_progress <= '1'; end if;
when "00001" => rddata_reg(0) <= spll_eccr_ext_en_int;
if (wb_we_i = '1') then rddata_reg(1) <= regs_i.eccr_ext_supported_i;
spll_eccr_ext_en_int <= wrdata_reg(0); rddata_reg(2) <= spll_eccr_align_en_int;
spll_eccr_align_en_int <= wrdata_reg(2); rddata_reg(3) <= regs_i.eccr_align_done_i;
end if; rddata_reg(4) <= regs_i.eccr_ext_ref_present_i;
rddata_reg(0) <= spll_eccr_ext_en_int; rddata_reg(5) <= 'X';
rddata_reg(1) <= regs_i.eccr_ext_supported_i; rddata_reg(6) <= 'X';
rddata_reg(2) <= spll_eccr_align_en_int; rddata_reg(7) <= 'X';
rddata_reg(3) <= regs_i.eccr_align_done_i; rddata_reg(8) <= 'X';
rddata_reg(4) <= regs_i.eccr_ext_ref_present_i; rddata_reg(9) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(11) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(12) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(13) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(16) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(17) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "00100" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; spll_occr_out_lock_int <= wrdata_reg(15 downto 8);
ack_sreg(0) <= '1'; end if;
ack_in_progress <= '1'; rddata_reg(7 downto 0) <= regs_i.occr_out_en_i;
when "00010" => rddata_reg(15 downto 8) <= spll_occr_out_lock_int;
if (wb_we_i = '1') then rddata_reg(23 downto 16) <= regs_i.occr_out_det_type_i;
spll_occr_out_lock_int <= wrdata_reg(15 downto 8); rddata_reg(24) <= 'X';
end if; rddata_reg(25) <= 'X';
rddata_reg(7 downto 0) <= regs_i.occr_out_en_i; rddata_reg(26) <= 'X';
rddata_reg(15 downto 8) <= spll_occr_out_lock_int; rddata_reg(27) <= 'X';
rddata_reg(23 downto 16) <= regs_i.occr_out_det_type_i; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "00101" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; regs_o.rcer_load_o <= '1';
ack_sreg(0) <= '1'; end if;
ack_in_progress <= '1'; rddata_reg(31 downto 0) <= regs_i.rcer_i;
when "00011" => ack_sreg(0) <= '1';
if (wb_we_i = '1') then ack_in_progress <= '1';
regs_o.rcer_load_o <= '1'; when "00110" =>
end if; if (wb_we_i = '1') then
rddata_reg(31 downto 0) <= regs_i.rcer_i; regs_o.ocer_load_o <= '1';
ack_sreg(0) <= '1'; end if;
ack_in_progress <= '1'; rddata_reg(7 downto 0) <= regs_i.ocer_i;
when "00100" => rddata_reg(8) <= 'X';
if (wb_we_i = '1') then rddata_reg(9) <= 'X';
regs_o.ocer_load_o <= '1'; rddata_reg(10) <= 'X';
end if; rddata_reg(11) <= 'X';
rddata_reg(7 downto 0) <= regs_i.ocer_i; rddata_reg(12) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(13) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(16) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(17) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "01000" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; regs_o.dac_hpll_wr_o <= '1';
ack_sreg(0) <= '1'; end if;
ack_in_progress <= '1'; rddata_reg(0) <= 'X';
when "00101" => rddata_reg(1) <= 'X';
if (wb_we_i = '1') then rddata_reg(2) <= 'X';
regs_o.dac_hpll_wr_o <= '1'; rddata_reg(3) <= 'X';
end if; rddata_reg(4) <= 'X';
rddata_reg(0) <= 'X'; rddata_reg(5) <= 'X';
rddata_reg(1) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(2) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(8) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(11) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(12) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(13) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(16) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(17) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "01001" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; regs_o.dac_main_value_wr_o <= '1';
ack_sreg(0) <= '1'; regs_o.dac_main_dac_sel_wr_o <= '1';
ack_in_progress <= '1'; end if;
when "00110" => rddata_reg(0) <= 'X';
if (wb_we_i = '1') then rddata_reg(1) <= 'X';
regs_o.dac_main_value_wr_o <= '1'; rddata_reg(2) <= 'X';
regs_o.dac_main_dac_sel_wr_o <= '1'; rddata_reg(3) <= 'X';
end if; rddata_reg(4) <= 'X';
rddata_reg(0) <= 'X'; rddata_reg(5) <= 'X';
rddata_reg(1) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(2) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(8) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(11) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(12) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(13) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(16) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(17) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "01010" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; spll_deglitch_thr_int <= wrdata_reg(15 downto 0);
ack_sreg(0) <= '1'; end if;
ack_in_progress <= '1'; rddata_reg(15 downto 0) <= spll_deglitch_thr_int;
when "00111" => rddata_reg(16) <= 'X';
if (wb_we_i = '1') then rddata_reg(17) <= 'X';
spll_deglitch_thr_int <= wrdata_reg(15 downto 0); rddata_reg(18) <= 'X';
end if; rddata_reg(19) <= 'X';
rddata_reg(15 downto 0) <= spll_deglitch_thr_int; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "01011" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; regs_o.dfr_spll_value_wr_o <= '1';
ack_sreg(0) <= '1'; regs_o.dfr_spll_eos_wr_o <= '1';
ack_in_progress <= '1'; end if;
when "01000" => rddata_reg(0) <= 'X';
if (wb_we_i = '1') then rddata_reg(1) <= 'X';
regs_o.dfr_spll_value_wr_o <= '1'; rddata_reg(2) <= 'X';
regs_o.dfr_spll_eos_wr_o <= '1'; rddata_reg(3) <= 'X';
end if; rddata_reg(4) <= 'X';
rddata_reg(0) <= 'X'; rddata_reg(5) <= 'X';
rddata_reg(1) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(2) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(8) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(11) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(12) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(13) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(16) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(17) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "01100" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; regs_o.crr_in_load_o <= '1';
ack_sreg(0) <= '1'; end if;
ack_in_progress <= '1'; rddata_reg(31 downto 0) <= regs_i.crr_in_i;
when "01001" => ack_sreg(0) <= '1';
if (wb_we_i = '1') then ack_in_progress <= '1';
regs_o.crr_in_load_o <= '1'; when "01101" =>
end if; if (wb_we_i = '1') then
rddata_reg(31 downto 0) <= regs_i.crr_in_i; regs_o.crr_out_load_o <= '1';
ack_sreg(0) <= '1'; end if;
ack_in_progress <= '1'; rddata_reg(15 downto 0) <= regs_i.crr_out_i;
when "01010" => rddata_reg(16) <= 'X';
if (wb_we_i = '1') then rddata_reg(17) <= 'X';
regs_o.crr_out_load_o <= '1'; rddata_reg(18) <= 'X';
end if; rddata_reg(19) <= 'X';
rddata_reg(15 downto 0) <= regs_i.crr_out_i; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "01110" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; regs_o.aux_cr_aux_sel_wr_o <= '1';
ack_sreg(0) <= '1'; regs_o.aux_cr_div_ref_wr_o <= '1';
ack_in_progress <= '1'; regs_o.aux_cr_div_fb_wr_o <= '1';
when "01011" => regs_o.aux_cr_gate_wr_o <= '1';
if (wb_we_i = '1') then end if;
regs_o.aux_cr_aux_sel_wr_o <= '1'; rddata_reg(0) <= 'X';
regs_o.aux_cr_div_ref_wr_o <= '1'; rddata_reg(1) <= 'X';
regs_o.aux_cr_div_fb_wr_o <= '1'; rddata_reg(2) <= 'X';
regs_o.aux_cr_gate_wr_o <= '1'; rddata_reg(3) <= 'X';
end if; rddata_reg(4) <= 'X';
rddata_reg(0) <= 'X'; rddata_reg(5) <= 'X';
rddata_reg(1) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(2) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(8) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(11) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(12) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(13) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(16) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(17) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "10000" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; eic_idr_write_int <= '1';
ack_sreg(0) <= '1'; end if;
ack_in_progress <= '1'; rddata_reg(0) <= 'X';
when "10000" => rddata_reg(1) <= 'X';
if (wb_we_i = '1') then rddata_reg(2) <= 'X';
eic_idr_write_int <= '1'; rddata_reg(3) <= 'X';
end if; rddata_reg(4) <= 'X';
rddata_reg(0) <= 'X'; rddata_reg(5) <= 'X';
rddata_reg(1) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(2) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(8) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(11) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(12) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(13) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(16) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(17) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(27) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(28) <= 'X'; ack_in_progress <= '1';
rddata_reg(29) <= 'X'; when "10001" =>
rddata_reg(30) <= 'X'; if (wb_we_i = '1') then
rddata_reg(31) <= 'X'; eic_ier_write_int <= '1';
ack_sreg(0) <= '1'; end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= eic_imr_int(0);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(0) <= eic_isr_status_int(0);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
end if;
if (spll_dfr_host_rdreq_int_d0 = '0') then
spll_dfr_host_rdreq_int <= not spll_dfr_host_rdreq_int;
else
rddata_reg(31 downto 0) <= spll_dfr_host_out_int(31 downto 0);
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10001" => ack_sreg(0) <= '1';
if (wb_we_i = '1') then end if;
eic_ier_write_int <= '1'; when "10101" =>
end if; if (wb_we_i = '1') then
rddata_reg(0) <= 'X'; end if;
rddata_reg(1) <= 'X'; rddata_reg(15 downto 0) <= spll_dfr_host_out_int(47 downto 32);
rddata_reg(2) <= 'X'; rddata_reg(16) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(17) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(31) <= 'X';
rddata_reg(18) <= 'X'; ack_sreg(0) <= '1';
rddata_reg(19) <= 'X'; ack_in_progress <= '1';
rddata_reg(20) <= 'X'; when "10110" =>
rddata_reg(21) <= 'X'; if (wb_we_i = '1') then
rddata_reg(22) <= 'X'; end if;
rddata_reg(23) <= 'X'; rddata_reg(16) <= spll_dfr_host_full_int;
rddata_reg(24) <= 'X'; rddata_reg(17) <= spll_dfr_host_empty_int;
rddata_reg(25) <= 'X'; rddata_reg(12 downto 0) <= spll_dfr_host_usedw_int;
rddata_reg(26) <= 'X'; rddata_reg(13) <= 'X';
rddata_reg(27) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(28) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(29) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(30) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(31) <= 'X'; rddata_reg(20) <= 'X';
ack_sreg(0) <= '1'; rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
if (wb_we_i = '1') then
end if;
if (spll_trr_rdreq_int_d0 = '0') then
spll_trr_rdreq_int <= not spll_trr_rdreq_int;
else
rddata_reg(23 downto 0) <= spll_trr_out_int(23 downto 0);
rddata_reg(30 downto 24) <= spll_trr_out_int(30 downto 24);
rddata_reg(31) <= spll_trr_out_int(31);
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10010" => ack_sreg(0) <= '1';
if (wb_we_i = '1') then end if;
end if; when "11000" =>
rddata_reg(0) <= eic_imr_int(0); if (wb_we_i = '1') then
rddata_reg(1) <= 'X'; end if;
rddata_reg(2) <= 'X'; rddata_reg(17) <= spll_trr_empty_int;
rddata_reg(3) <= 'X'; rddata_reg(0) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(1) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(2) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(3) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(4) <= 'X';
rddata_reg(8) <= 'X'; rddata_reg(5) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(8) <= 'X';
rddata_reg(12) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(13) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(14) <= 'X'; rddata_reg(11) <= 'X';
rddata_reg(15) <= 'X'; rddata_reg(12) <= 'X';
rddata_reg(16) <= 'X'; rddata_reg(13) <= 'X';
rddata_reg(17) <= 'X'; rddata_reg(14) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(15) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(16) <= 'X';
rddata_reg(20) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(21) <= 'X'; rddata_reg(19) <= 'X';
rddata_reg(22) <= 'X'; rddata_reg(20) <= 'X';
rddata_reg(23) <= 'X'; rddata_reg(21) <= 'X';
rddata_reg(24) <= 'X'; rddata_reg(22) <= 'X';
rddata_reg(25) <= 'X'; rddata_reg(23) <= 'X';
rddata_reg(26) <= 'X'; rddata_reg(24) <= 'X';
rddata_reg(27) <= 'X'; rddata_reg(25) <= 'X';
rddata_reg(28) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(29) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(30) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(31) <= 'X'; rddata_reg(29) <= 'X';
ack_sreg(0) <= '1'; rddata_reg(30) <= 'X';
ack_in_progress <= '1'; rddata_reg(31) <= 'X';
when "10011" => ack_sreg(0) <= '1';
if (wb_we_i = '1') then ack_in_progress <= '1';
eic_isr_write_int <= '1'; when others =>
end if;
rddata_reg(0) <= eic_isr_status_int(0);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
end if;
if (spll_dfr_host_rdreq_int_d0 = '0') then
spll_dfr_host_rdreq_int <= not spll_dfr_host_rdreq_int;
else
rddata_reg(31 downto 0) <= spll_dfr_host_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "10101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= spll_dfr_host_out_int(47 downto 32);
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= spll_dfr_host_full_int;
rddata_reg(17) <= spll_dfr_host_empty_int;
rddata_reg(12 downto 0) <= spll_dfr_host_usedw_int;
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
if (wb_we_i = '1') then
end if;
if (spll_trr_rdreq_int_d0 = '0') then
spll_trr_rdreq_int <= not spll_trr_rdreq_int;
else
rddata_reg(23 downto 0) <= spll_trr_out_int(23 downto 0);
rddata_reg(30 downto 24) <= spll_trr_out_int(30 downto 24);
rddata_reg(31) <= spll_trr_out_int(31);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "11000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(17) <= spll_trr_empty_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address -- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1'; ack_in_progress <= '1';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
end case; end case;
end if; end if;
end if; end if;
end if; end if;
end process; end process;
-- Drive the data output bus -- Drive the data output bus
wb_dat_o <= rddata_reg; wb_dat_o <= rddata_reg;
-- Number of reference channels (max: 32) -- Number of reference channels (max: 32)
-- Number of output channels (max: 8) -- Number of output channels (max: 8)
-- Debug queue supported -- Debug queue supported
-- Enable External Clock BB Detector -- Enable External Clock BB Detector
regs_o.eccr_ext_en_o <= spll_eccr_ext_en_int; regs_o.eccr_ext_en_o <= spll_eccr_ext_en_int;
-- External Clock Input Available -- External Clock Input Available
-- Enable PPS/phase alignment -- Enable PPS/phase alignment
regs_o.eccr_align_en_o <= spll_eccr_align_en_int; regs_o.eccr_align_en_o <= spll_eccr_align_en_int;
-- PPS/phase alignment done -- PPS/phase alignment done
-- External Clock Reference Present -- External Clock Reference Present
-- Output Channel HW enable flag -- Output Channel HW enable flag
-- Output Channel locked flag -- Output Channel locked flag
regs_o.occr_out_lock_o <= spll_occr_out_lock_int; regs_o.occr_out_lock_o <= spll_occr_out_lock_int;
-- Output Channel Phase Detector Type -- Output Channel Phase Detector Type
-- Reference Channel Enable -- Reference Channel Enable
regs_o.rcer_o <= wrdata_reg(31 downto 0); regs_o.rcer_o <= wrdata_reg(31 downto 0);
-- Output Channel Enable -- Output Channel Enable
regs_o.ocer_o <= wrdata_reg(7 downto 0); regs_o.ocer_o <= wrdata_reg(7 downto 0);
-- DAC value -- DAC value
-- pass-through field: DAC value in register: Helper DAC Output -- pass-through field: DAC value in register: Helper DAC Output
regs_o.dac_hpll_o <= wrdata_reg(15 downto 0); regs_o.dac_hpll_o <= wrdata_reg(15 downto 0);
-- DAC value -- DAC value
-- pass-through field: DAC value in register: Main DAC Output -- pass-through field: DAC value in register: Main DAC Output
regs_o.dac_main_value_o <= wrdata_reg(15 downto 0); regs_o.dac_main_value_o <= wrdata_reg(15 downto 0);
-- DAC select -- DAC select
-- pass-through field: DAC select in register: Main DAC Output -- pass-through field: DAC select in register: Main DAC Output
regs_o.dac_main_dac_sel_o <= wrdata_reg(19 downto 16); regs_o.dac_main_dac_sel_o <= wrdata_reg(19 downto 16);
-- Threshold -- Threshold
regs_o.deglitch_thr_o <= spll_deglitch_thr_int; regs_o.deglitch_thr_o <= spll_deglitch_thr_int;
-- Debug Value -- Debug Value
-- pass-through field: Debug Value in register: Debug FIFO Register - SPLL side -- pass-through field: Debug Value in register: Debug FIFO Register - SPLL side
regs_o.dfr_spll_value_o <= wrdata_reg(30 downto 0); regs_o.dfr_spll_value_o <= wrdata_reg(30 downto 0);
-- End-of-Sample -- End-of-Sample
-- pass-through field: End-of-Sample in register: Debug FIFO Register - SPLL side -- pass-through field: End-of-Sample in register: Debug FIFO Register - SPLL side
regs_o.dfr_spll_eos_o <= wrdata_reg(31); regs_o.dfr_spll_eos_o <= wrdata_reg(31);
-- Counter Resync -- Counter Resync
regs_o.crr_in_o <= wrdata_reg(31 downto 0); regs_o.crr_in_o <= wrdata_reg(31 downto 0);
-- Counter Resync -- Counter Resync
regs_o.crr_out_o <= wrdata_reg(15 downto 0); regs_o.crr_out_o <= wrdata_reg(15 downto 0);
-- Aux output select genblock_0: if (not (g_with_debug_fifo = 0)) generate
-- pass-through field: Aux output select in register: Aux clock configuration register
regs_o.aux_cr_aux_sel_o <= wrdata_reg(2 downto 0);
-- BB reference divider
-- pass-through field: BB reference divider in register: Aux clock configuration register
regs_o.aux_cr_div_ref_o <= wrdata_reg(8 downto 3);
-- BB feedback divider
-- pass-through field: BB feedback divider in register: Aux clock configuration register
regs_o.aux_cr_div_fb_o <= wrdata_reg(14 downto 9);
-- BB gating frequency select
-- pass-through field: BB gating frequency select in register: Aux clock configuration register
regs_o.aux_cr_gate_o <= wrdata_reg(18 downto 15);
genblock_0 : if (not (g_with_debug_fifo = 0)) generate
-- extra code for reg/fifo/mem: Debug FIFO Register - Host side -- extra code for reg/fifo/mem: Debug FIFO Register - Host side
spll_dfr_host_in_int(31 downto 0) <= regs_i.dfr_host_value_i; spll_dfr_host_in_int(31 downto 0) <= regs_i.dfr_host_value_i;
spll_dfr_host_in_int(47 downto 32) <= regs_i.dfr_host_seq_id_i; spll_dfr_host_in_int(47 downto 32) <= regs_i.dfr_host_seq_id_i;
spll_dfr_host_rst_n <= rst_n_i; spll_dfr_host_rst_n <= rst_n_i;
spll_dfr_host_INST : wbgen2_fifo_sync spll_dfr_host_INST : wbgen2_fifo_sync
generic map ( generic map (
g_size => 8192, g_size => 8192,
g_width => 48, g_width => 48,
g_usedw_size => 13 g_usedw_size => 13
) )
port map ( port map (
wr_req_i => regs_i.dfr_host_wr_req_i, wr_req_i => regs_i.dfr_host_wr_req_i,
wr_full_o => regs_o.dfr_host_wr_full_o, wr_full_o => regs_o.dfr_host_wr_full_o,
wr_empty_o => regs_o.dfr_host_wr_empty_o, wr_empty_o => regs_o.dfr_host_wr_empty_o,
wr_usedw_o => regs_o.dfr_host_wr_usedw_o, wr_usedw_o => regs_o.dfr_host_wr_usedw_o,
rd_full_o => spll_dfr_host_full_int, rd_full_o => spll_dfr_host_full_int,
rd_empty_o => spll_dfr_host_empty_int, rd_empty_o => spll_dfr_host_empty_int,
rd_usedw_o => spll_dfr_host_usedw_int, rd_usedw_o => spll_dfr_host_usedw_int,
rd_req_i => spll_dfr_host_rdreq_int, rd_req_i => spll_dfr_host_rdreq_int,
rst_n_i => spll_dfr_host_rst_n, rst_n_i => spll_dfr_host_rst_n,
clk_i => clk_sys_i, clk_i => clk_sys_i,
wr_data_i => spll_dfr_host_in_int, wr_data_i => spll_dfr_host_in_int,
rd_data_o => spll_dfr_host_out_int rd_data_o => spll_dfr_host_out_int
); );
end generate genblock_0; end generate genblock_0;
-- extra code for reg/fifo/mem: Tag Readout Register -- extra code for reg/fifo/mem: Tag Readout Register
spll_trr_in_int(23 downto 0) <= regs_i.trr_value_i; spll_trr_in_int(23 downto 0) <= regs_i.trr_value_i;
spll_trr_in_int(30 downto 24) <= regs_i.trr_chan_id_i; spll_trr_in_int(30 downto 24) <= regs_i.trr_chan_id_i;
spll_trr_in_int(31) <= regs_i.trr_disc_i; spll_trr_in_int(31) <= regs_i.trr_disc_i;
spll_trr_rst_n <= rst_n_i; spll_trr_rst_n <= rst_n_i;
spll_trr_INST : wbgen2_fifo_sync spll_trr_INST : wbgen2_fifo_sync
generic map ( generic map (
g_size => 32, g_size => 32,
g_width => 32, g_width => 32,
g_usedw_size => 5 g_usedw_size => 5
) )
port map ( port map (
wr_req_i => regs_i.trr_wr_req_i, wr_req_i => regs_i.trr_wr_req_i,
wr_full_o => regs_o.trr_wr_full_o, wr_full_o => regs_o.trr_wr_full_o,
wr_empty_o => regs_o.trr_wr_empty_o, wr_empty_o => regs_o.trr_wr_empty_o,
rd_empty_o => spll_trr_empty_int, rd_empty_o => spll_trr_empty_int,
rd_req_i => spll_trr_rdreq_int, rd_req_i => spll_trr_rdreq_int,
rst_n_i => spll_trr_rst_n, rst_n_i => spll_trr_rst_n,
clk_i => clk_sys_i, clk_i => clk_sys_i,
wr_data_i => spll_trr_in_int, wr_data_i => spll_trr_in_int,
rd_data_o => spll_trr_out_int rd_data_o => spll_trr_out_int
); );
-- Aux output select
-- pass-through field: Aux output select in register: Aux clock configuration register
regs_o.aux_cr_aux_sel_o <= wrdata_reg(2 downto 0);
-- BB reference divider
-- pass-through field: BB reference divider in register: Aux clock configuration register
regs_o.aux_cr_div_ref_o <= wrdata_reg(8 downto 3);
-- BB feedback divider
-- pass-through field: BB feedback divider in register: Aux clock configuration register
regs_o.aux_cr_div_fb_o <= wrdata_reg(14 downto 9);
-- BB gating frequency select
-- pass-through field: BB gating frequency select in register: Aux clock configuration register
regs_o.aux_cr_gate_o <= wrdata_reg(18 downto 15);
-- extra code for reg/fifo/mem: Interrupt disable register -- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(0) <= wrdata_reg(0); eic_idr_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt enable register -- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(0) <= wrdata_reg(0); eic_ier_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt status register -- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(0) <= wrdata_reg(0); eic_isr_clear_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER -- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic eic_irq_controller_inst : wbgen2_eic
generic map ( generic map (
g_num_interrupts => 1, g_num_interrupts => 1,
g_irq00_mode => 3, g_irq00_mode => 3,
g_irq01_mode => 0, g_irq01_mode => 0,
g_irq02_mode => 0, g_irq02_mode => 0,
g_irq03_mode => 0, g_irq03_mode => 0,
g_irq04_mode => 0, g_irq04_mode => 0,
g_irq05_mode => 0, g_irq05_mode => 0,
g_irq06_mode => 0, g_irq06_mode => 0,
g_irq07_mode => 0, g_irq07_mode => 0,
g_irq08_mode => 0, g_irq08_mode => 0,
g_irq09_mode => 0, g_irq09_mode => 0,
g_irq0a_mode => 0, g_irq0a_mode => 0,
g_irq0b_mode => 0, g_irq0b_mode => 0,
g_irq0c_mode => 0, g_irq0c_mode => 0,
g_irq0d_mode => 0, g_irq0d_mode => 0,
g_irq0e_mode => 0, g_irq0e_mode => 0,
g_irq0f_mode => 0, g_irq0f_mode => 0,
g_irq10_mode => 0, g_irq10_mode => 0,
g_irq11_mode => 0, g_irq11_mode => 0,
g_irq12_mode => 0, g_irq12_mode => 0,
g_irq13_mode => 0, g_irq13_mode => 0,
g_irq14_mode => 0, g_irq14_mode => 0,
g_irq15_mode => 0, g_irq15_mode => 0,
g_irq16_mode => 0, g_irq16_mode => 0,
g_irq17_mode => 0, g_irq17_mode => 0,
g_irq18_mode => 0, g_irq18_mode => 0,
g_irq19_mode => 0, g_irq19_mode => 0,
g_irq1a_mode => 0, g_irq1a_mode => 0,
g_irq1b_mode => 0, g_irq1b_mode => 0,
g_irq1c_mode => 0, g_irq1c_mode => 0,
g_irq1d_mode => 0, g_irq1d_mode => 0,
g_irq1e_mode => 0, g_irq1e_mode => 0,
g_irq1f_mode => 0 g_irq1f_mode => 0
) )
port map ( port map (
clk_i => clk_sys_i, clk_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int, irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int, irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int, reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int, reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int, reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int, reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int, reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int, reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int, reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int, reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o wb_irq_o => wb_int_o
); );
irq_inputs_vector_int(0) <= irq_tag_i; irq_inputs_vector_int(0) <= irq_tag_i;
-- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 0 -- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 0
process (clk_sys_i, rst_n_i) process (clk_sys_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
spll_dfr_host_rdreq_int_d0 <= '0'; spll_dfr_host_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
spll_dfr_host_rdreq_int_d0 <= spll_dfr_host_rdreq_int; spll_dfr_host_rdreq_int_d0 <= spll_dfr_host_rdreq_int;
end if; end if;
end process; end process;
-- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 1 -- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Tag Readout Register' data output register 0 -- extra code for reg/fifo/mem: FIFO 'Tag Readout Register' data output register 0
process (clk_sys_i, rst_n_i) process (clk_sys_i, rst_n_i)
begin begin
if (rst_n_i = '0') then if (rst_n_i = '0') then
spll_trr_rdreq_int_d0 <= '0'; spll_trr_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
spll_trr_rdreq_int_d0 <= spll_trr_rdreq_int; spll_trr_rdreq_int_d0 <= spll_trr_rdreq_int;
end if; end if;
end process; end process;
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0); wb_ack_o <= ack_sreg(0);
end syn; end syn;
modules/wr_softpll_ng/spll_wb_slave.wb
View file @ 52a169e7
...@@ -9,6 +9,15 @@ peripheral { ...@@ -9,6 +9,15 @@ peripheral {
name = "SPLL Control/Status Register"; name = "SPLL Control/Status Register";
prefix = "CSR"; prefix = "CSR";
field {
align = 8;
name = "Unused (kept for software compatibility).";
prefix = "UNUSED0";
size = 6;
type = CONSTANT;
value = 0;
};
field { field {
align = 8; align = 8;
...@@ -101,6 +110,7 @@ peripheral { ...@@ -101,6 +110,7 @@ peripheral {
}; };
reg { reg {
align = 4;
name = "Output Channel Control Register"; name = "Output Channel Control Register";
prefix = "OCCR"; prefix = "OCCR";
...@@ -167,6 +177,7 @@ peripheral { ...@@ -167,6 +177,7 @@ peripheral {
}; };
reg { reg {
align = 8;
name = "Helper DAC Output"; name = "Helper DAC Output";
prefix = "DAC_HPLL"; prefix = "DAC_HPLL";
...@@ -263,43 +274,7 @@ peripheral { ...@@ -263,43 +274,7 @@ peripheral {
}; };
}; };
reg { fifo_reg {
name = "Aux clock configuration register";
prefix = "AUX_CR";
field {
name = "Aux output select";
prefix = "AUX_SEL";
size = 3;
type = PASS_THROUGH;
};
field {
name = "BB reference divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_REF";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB feedback divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_FB";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB gating frequency select";
description = "BB detector output gating frequency. GATE = log2(period in clk_ref cycles).";
prefix = "GATE";
size = 4;
type = PASS_THROUGH;
};
};
fifo_reg {
name = "Debug FIFO Register - Host side"; name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST"; prefix = "DFR_HOST";
direction = CORE_TO_BUS; direction = CORE_TO_BUS;
...@@ -356,6 +331,42 @@ peripheral { ...@@ -356,6 +331,42 @@ peripheral {
}; };
}; };
reg {
name = "Aux clock configuration register";
prefix = "AUX_CR";
field {
name = "Aux output select";
prefix = "AUX_SEL";
size = 3;
type = PASS_THROUGH;
};
field {
name = "BB reference divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_REF";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB feedback divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_FB";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB gating frequency select";
description = "BB detector output gating frequency. GATE = log2(period in clk_ref cycles).";
prefix = "GATE";
size = 4;
type = PASS_THROUGH;
};
};
irq { irq {
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ 52a169e7
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd -- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb -- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Wed Mar 20 10:53:43 2013 -- Created : Thu Jul 25 11:14:53 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
...@@ -89,6 +89,11 @@ package spll_wbgen2_pkg is ...@@ -89,6 +89,11 @@ package spll_wbgen2_pkg is
crr_in_load_o : std_logic; crr_in_load_o : std_logic;
crr_out_o : std_logic_vector(15 downto 0); crr_out_o : std_logic_vector(15 downto 0);
crr_out_load_o : std_logic; crr_out_load_o : std_logic;
dfr_host_wr_full_o : std_logic;
dfr_host_wr_empty_o : std_logic;
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic;
aux_cr_aux_sel_o : std_logic_vector(2 downto 0); aux_cr_aux_sel_o : std_logic_vector(2 downto 0);
aux_cr_aux_sel_wr_o : std_logic; aux_cr_aux_sel_wr_o : std_logic;
aux_cr_div_ref_o : std_logic_vector(5 downto 0); aux_cr_div_ref_o : std_logic_vector(5 downto 0);
...@@ -97,11 +102,6 @@ package spll_wbgen2_pkg is ...@@ -97,11 +102,6 @@ package spll_wbgen2_pkg is
aux_cr_div_fb_wr_o : std_logic; aux_cr_div_fb_wr_o : std_logic;
aux_cr_gate_o : std_logic_vector(3 downto 0); aux_cr_gate_o : std_logic_vector(3 downto 0);
aux_cr_gate_wr_o : std_logic; aux_cr_gate_wr_o : std_logic;
dfr_host_wr_full_o : std_logic;
dfr_host_wr_empty_o : std_logic;
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic;
end record; end record;
constant c_spll_out_registers_init_value: t_spll_out_registers := ( constant c_spll_out_registers_init_value: t_spll_out_registers := (
...@@ -127,6 +127,11 @@ package spll_wbgen2_pkg is ...@@ -127,6 +127,11 @@ package spll_wbgen2_pkg is
crr_in_load_o => '0', crr_in_load_o => '0',
crr_out_o => (others => '0'), crr_out_o => (others => '0'),
crr_out_load_o => '0', crr_out_load_o => '0',
dfr_host_wr_full_o => '0',
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0',
trr_wr_empty_o => '0',
aux_cr_aux_sel_o => (others => '0'), aux_cr_aux_sel_o => (others => '0'),
aux_cr_aux_sel_wr_o => '0', aux_cr_aux_sel_wr_o => '0',
aux_cr_div_ref_o => (others => '0'), aux_cr_div_ref_o => (others => '0'),
...@@ -134,12 +139,7 @@ package spll_wbgen2_pkg is ...@@ -134,12 +139,7 @@ package spll_wbgen2_pkg is
aux_cr_div_fb_o => (others => '0'), aux_cr_div_fb_o => (others => '0'),
aux_cr_div_fb_wr_o => '0', aux_cr_div_fb_wr_o => '0',
aux_cr_gate_o => (others => '0'), aux_cr_gate_o => (others => '0'),
aux_cr_gate_wr_o => '0', aux_cr_gate_wr_o => '0'
dfr_host_wr_full_o => '0',
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0',
trr_wr_empty_o => '0'
); );
function "or" (left, right: t_spll_in_registers) return t_spll_in_registers; function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
function f_x_to_zero (x:std_logic) return std_logic; function f_x_to_zero (x:std_logic) return std_logic;
......
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ 52a169e7
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski -- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2011-01-29 -- Created : 2011-01-29
-- Last update: 2013-03-20 -- Last update: 2013-07-25
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
......
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ 52a169e7
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski -- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2011-01-29 -- Created : 2011-01-29
-- Last update: 2013-03-20 -- Last update: 2013-07-25
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
......
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