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White Rabbit core collection
Commit 52a169e7 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_softpll_ng: make new register layout compatible with the previous version of SoftPLL

parent 120c203d
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Showing with 888 additions and 882 deletions
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ 52a169e7
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modules/wr_softpll_ng/spll_wb_slave.wb
View file @ 52a169e7
......@@ -9,6 +9,15 @@ peripheral {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
align = 8;
name = "Unused (kept for software compatibility).";
prefix = "UNUSED0";
size = 6;
type = CONSTANT;
value = 0;
};
field {
align = 8;
......@@ -101,6 +110,7 @@ peripheral {
};
reg {
align = 4;
name = "Output Channel Control Register";
prefix = "OCCR";
......@@ -167,6 +177,7 @@ peripheral {
};
reg {
align = 8;
name = "Helper DAC Output";
prefix = "DAC_HPLL";
......@@ -263,43 +274,7 @@ peripheral {
};
};
reg {
name = "Aux clock configuration register";
prefix = "AUX_CR";
field {
name = "Aux output select";
prefix = "AUX_SEL";
size = 3;
type = PASS_THROUGH;
};
field {
name = "BB reference divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_REF";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB feedback divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_FB";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB gating frequency select";
description = "BB detector output gating frequency. GATE = log2(period in clk_ref cycles).";
prefix = "GATE";
size = 4;
type = PASS_THROUGH;
};
};
fifo_reg {
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
......@@ -356,6 +331,42 @@ peripheral {
};
};
reg {
name = "Aux clock configuration register";
prefix = "AUX_CR";
field {
name = "Aux output select";
prefix = "AUX_SEL";
size = 3;
type = PASS_THROUGH;
};
field {
name = "BB reference divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_REF";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB feedback divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_FB";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB gating frequency select";
description = "BB detector output gating frequency. GATE = log2(period in clk_ref cycles).";
prefix = "GATE";
size = 4;
type = PASS_THROUGH;
};
};
irq {
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ 52a169e7
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Wed Mar 20 10:53:43 2013
-- Created : Thu Jul 25 11:14:53 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -89,6 +89,11 @@ package spll_wbgen2_pkg is
crr_in_load_o : std_logic;
crr_out_o : std_logic_vector(15 downto 0);
crr_out_load_o : std_logic;
dfr_host_wr_full_o : std_logic;
dfr_host_wr_empty_o : std_logic;
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic;
aux_cr_aux_sel_o : std_logic_vector(2 downto 0);
aux_cr_aux_sel_wr_o : std_logic;
aux_cr_div_ref_o : std_logic_vector(5 downto 0);
......@@ -97,11 +102,6 @@ package spll_wbgen2_pkg is
aux_cr_div_fb_wr_o : std_logic;
aux_cr_gate_o : std_logic_vector(3 downto 0);
aux_cr_gate_wr_o : std_logic;
dfr_host_wr_full_o : std_logic;
dfr_host_wr_empty_o : std_logic;
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic;
end record;
constant c_spll_out_registers_init_value: t_spll_out_registers := (
......@@ -127,6 +127,11 @@ package spll_wbgen2_pkg is
crr_in_load_o => '0',
crr_out_o => (others => '0'),
crr_out_load_o => '0',
dfr_host_wr_full_o => '0',
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0',
trr_wr_empty_o => '0',
aux_cr_aux_sel_o => (others => '0'),
aux_cr_aux_sel_wr_o => '0',
aux_cr_div_ref_o => (others => '0'),
......@@ -134,12 +139,7 @@ package spll_wbgen2_pkg is
aux_cr_div_fb_o => (others => '0'),
aux_cr_div_fb_wr_o => '0',
aux_cr_gate_o => (others => '0'),
aux_cr_gate_wr_o => '0',
dfr_host_wr_full_o => '0',
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0',
trr_wr_empty_o => '0'
aux_cr_gate_wr_o => '0'
);
function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ 52a169e7
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2013-03-20
-- Last update: 2013-07-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ 52a169e7
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2013-03-20
-- Last update: 2013-07-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......
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