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White Rabbit core collection
Commit 535518a0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_core: drive unused ack/err/rty wishbone signals to safe values

parent fbfe9bc0
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Showing with 51 additions and 7 deletions
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 535518a0
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-04-23
-- Last update: 2012-07-09
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -280,6 +280,10 @@ begin
led_link_o => led_link_o,
led_act_o => led_act_o);
wb_o.err <= '0';
wb_o.rty <= '0';
wb_o.int <= '0';
end syn;
modules/wr_mini_nic/xwr_mini_nic.vhd
View file @ 535518a0
......@@ -158,4 +158,8 @@ begin -- wrapper
wb_stall_o => wb_o.stall,
wb_irq_o => wb_o.int);
wb_o.err <= '0';
wb_o.rty <= '0';
end wrapper;
modules/wr_pps_gen/xwr_pps_gen.vhd
View file @ 535518a0
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2012-04-13
-- Last update: 2012-07-09
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -130,4 +130,8 @@ begin -- behavioral
);
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <= '0';
end behavioral;
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ 535518a0
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2012-04-30
-- Last update: 2012-07-09
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -238,4 +238,8 @@ begin -- behavioral
debug_o => debug_o,
dbg_fifo_irq_o => dbg_fifo_irq_o);
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <= '0';
end wrapper;
modules/wrc_core/wr_core.vhd
View file @ 535518a0
......@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2012-06-15
-- Last update: 2012-07-09
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -879,6 +879,24 @@ begin
secbar_master_i(7).err <= '0';
secbar_master_i(7).rty <= '0';
--secbar_master_i(6).err <= '0';
--secbar_master_i(5).err <= '0';
--secbar_master_i(4).err <= '0';
--secbar_master_i(3).err <= '0';
--secbar_master_i(2).err <= '0';
--secbar_master_i(1).err <= '0';
--secbar_master_i(0).err <= '0';
--secbar_master_i(6).rty <= '0';
--secbar_master_i(5).rty <= '0';
--secbar_master_i(4).rty <= '0';
--secbar_master_i(3).rty <= '0';
--secbar_master_i(2).rty <= '0';
--secbar_master_i(1).rty <= '0';
--secbar_master_i(0).rty <= '0';
-----------------------------------------------------------------------------
-- WBP MUX
-----------------------------------------------------------------------------
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 535518a0
......@@ -307,6 +307,10 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
);
end component;
constant cc_unused_master_in : t_wishbone_master_in :=
('1', '0', '0', '0', '0', cc_dummy_data);
-----------------------------------------------------------------------------
-- Public WR component definitions
-----------------------------------------------------------------------------
......@@ -376,7 +380,7 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
slave_o : out t_wishbone_slave_out;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
aux_master_i : in t_wishbone_master_in := cc_unused_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
......
modules/wrc_core/xwr_core.vhd
View file @ 535518a0
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2012-06-15
-- Last update: 2012-07-09
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......
modules/wrc_core/xwr_syscon_wb.vhd
View file @ 535518a0
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-11-07
-- Last update: 2011-11-07
-- Last update: 2012-07-09
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -108,4 +108,10 @@ begin
wb_in.adr(c_wishbone_address_width-1 downto 3) <= (others=>'0');
slave_o.err <= '0';
slave_o.rty <= '0';
end syn;
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