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White Rabbit core collection
Commit 53a876b4 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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eca2: reconfig max delay

parent 9e8ba342
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Showing with 20 additions and 606 deletions
modules/wr_eca/eca_channel.vhd deleted 100644 → 0
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modules/wr_eca/eca_internals_pkg.vhd
View file @ 53a876b4
......@@ -295,6 +295,7 @@ package eca_internals_pkg is
g_ext_size : natural; -- extra bits tracked by scanner
g_log_size : natural; -- 2**g_log_size = buffer entries
g_log_multiplier : natural; -- 2**g_log_multiplier = ticks per cycle
g_log_max_delay : natural; -- 2**g_log_max_delay = maximum delay before executed as early
g_log_latency : natural);-- 2**g_log_latency = ticks of calendar delay
port(
clk_i : in std_logic;
......@@ -329,6 +330,7 @@ package eca_internals_pkg is
generic(
g_log_size : natural := 8; -- 2**g_log_size = maximum number of pending actions
g_log_multiplier : natural := 3; -- 2**g_log_multiplier = ticks per cycle
g_log_max_delay : natural := 32; -- 2**g_log_max_delay = maximum delay before executed as early
g_log_latency : natural := 12);-- 2**g_log_latency = ticks of calendar delay
port(
clk_i : in std_logic;
......
modules/wr_eca/eca_scan.vhd
View file @ 53a876b4
......@@ -36,6 +36,7 @@ entity eca_scan is
g_ext_size : natural; -- extra bits tracked by scanner
g_log_size : natural; -- 2**g_log_size = buffer entries
g_log_multiplier : natural; -- 2**g_log_multiplier = ticks per cycle
g_log_max_delay : natural; -- 2**g_log_max_delay = maximum delay before executed as early
g_log_latency : natural);-- 2**g_log_latency = ticks of calendar delay
port(
clk_i : in std_logic;
......@@ -59,14 +60,14 @@ end eca_scan;
architecture rtl of eca_scan is
constant c_log_cap : natural := 30; -- Maximum ticks an action can be delayed
constant c_log_count : natural := c_log_cap - g_log_latency;
constant c_log_count : natural := g_log_max_delay - g_log_latency;
constant c_multiplier1_bits : std_logic_vector(g_log_multiplier downto 0) := (others => '0');
-- Fields in the table
constant c_valid : natural := 0;
constant c_late : natural := 1;
constant c_early : natural := 2;
-- subtype c_ext is natural range x downto x;
constant c_ext : std_logic_vector(g_ext_size +c_early downto c_early +1) := (others => '0');
constant c_low : std_logic_vector(g_log_latency+c_ext'high downto c_ext'high+1) := (others => '0');
constant c_count : std_logic_vector(c_log_count +c_low'high downto c_low'high+1) := (others => '0');
......@@ -221,13 +222,13 @@ begin
end process;
s_late3 <= r_count3(time_i'length);
s_early3 <= f_eca_or(r_count3(time_i'high downto c_log_cap)) and not s_late3;
s_early3 <= f_eca_or(r_count3(time_i'high downto g_log_max_delay)) and not s_late3;
-- Saturate the counter calculation
s_count3 <=
(others => '0') when s_late3 ='1' else
(others => '1') when s_early3='1' else
r_count3(c_log_cap-1 downto g_log_latency);
r_count3(g_log_max_delay-1 downto g_log_latency);
-- Write-write race is prevented by never writing-back something not valid
-- ... and we know that scan is never asked to write to something already valid
......
modules/wr_eca/eca_scan_tb.vhd
View file @ 53a876b4
......@@ -41,6 +41,7 @@ architecture rtl of eca_scan_tb is
constant c_log_size : natural := 1 + g_case; -- smaller => tests edge cases better
constant c_log_multiplier : natural := g_case mod 3;
constant c_log_latency : natural := c_log_size + c_log_multiplier + 1;
constant c_log_max_delay : natural := 32;
signal r_time : t_time := (others => '0');
signal r_wen : std_logic := '0';
......@@ -63,6 +64,7 @@ begin
g_ext_size => c_ext_size,
g_log_size => c_log_size,
g_log_multiplier => c_log_multiplier,
g_log_max_delay => c_log_max_delay,
g_log_latency => c_log_latency)
port map(
clk_i => clk_i,
......
modules/wr_eca/eca_sdp.vhd
View file @ 53a876b4
......@@ -51,12 +51,11 @@ end eca_sdp;
architecture rtl of eca_sdp is
constant c_depth : natural := 2**g_addr_bits;
constant c_undef : std_logic_vector(g_data_bits-1 downto 0) := (others => 'X');
type t_memory is array(c_depth-1 downto 0) of std_logic_vector(g_data_bits-1 downto 0);
signal r_memory : t_memory := (others => (others => '-'));
signal r_bypass : std_logic := '0';
signal w_data : std_logic_vector(g_data_bits-1 downto 0);
signal w_data : std_logic_vector(g_data_bits-1 downto 0) := (others => 'X');
signal r_data : std_logic_vector(g_data_bits-1 downto 0);
begin
......@@ -74,7 +73,10 @@ begin
assert f_eca_safe(w_addr_i) = '1' report "Attempt to write to a meta-values address" severity failure;
r_memory(to_integer(unsigned(w_addr_i))) <= w_data_i;
end if;
w_data <= w_data_i;
if g_bypass then
w_data <= w_data_i;
end if;
end if;
end process;
......@@ -91,11 +93,6 @@ begin
end if;
end process;
bypass : if g_bypass generate
r_data_o <= f_eca_mux(r_bypass, w_data, r_data);
end generate;
undef : if not g_bypass generate
r_data_o <= f_eca_mux(r_bypass, c_undef, r_data);
end generate;
r_data_o <= f_eca_mux(r_bypass, w_data, r_data);
end rtl;
modules/wr_eca/eca_tag_channel.vhd
View file @ 53a876b4
......@@ -32,6 +32,7 @@ entity eca_tag_channel is
generic(
g_log_size : natural := 8; -- 2**g_log_size = maximum number of pending actions
g_log_multiplier : natural := 3; -- 2**g_log_multiplier = ticks per cycle
g_log_max_delay : natural := 32; -- 2**g_log_max_delay = maximum delay before executed as early
g_log_latency : natural := 12);-- 2**g_log_latency = ticks of calendar delay
port(
clk_i : in std_logic;
......@@ -223,6 +224,7 @@ begin
g_ext_size => 1,
g_log_size => c_log_scan_size,
g_log_multiplier => g_log_multiplier,
g_log_max_delay => g_log_max_delay,
g_log_latency => g_log_latency)
port map(
clk_i => clk_i,
......@@ -392,6 +394,7 @@ begin
clk_i => clk_i,
rst_n_i => rst_n_i,
push_i => s_com_valid_o(0),
full_o => open,
data_i => s_fifo_masked,
pop_i => s_fifo_pop,
valid_o => s_fifo_valid,
......
modules/wr_eca/eca_tag_channel_tb.vhd
View file @ 53a876b4
......@@ -40,6 +40,7 @@ architecture rtl of eca_tag_channel_tb is
constant c_log_size : natural := 1 + g_case; -- smaller => tests edge cases better
constant c_log_multiplier : natural := g_case mod 3;
constant c_log_latency : natural := c_log_size + c_log_multiplier; -- !!! test: +1,0,-1
constant c_log_max_delay : natural := c_log_latency+2;
constant c_ticks : natural := 2**c_log_multiplier;
signal r_time : t_time := (others => '0');
......@@ -53,6 +54,7 @@ begin
generic map(
g_log_size => c_log_size,
g_log_multiplier => c_log_multiplier,
g_log_max_delay => c_log_max_delay,
g_log_latency => c_log_latency)
port map(
clk_i => clk_i,
......
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