timing/hpll_period_detect: removed async reset

57573d98 · Tomasz Wlostowski · 879a9b30 · 57573d98
Commit 57573d98 authored Nov 03, 2011 by Tomasz Wlostowski
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hpll_period_detect.vhd modules/timing/hpll_period_detect.vhd +2 -2

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--- a/modules/timing/hpll_period_detect.vhd
+++ b/modules/timing/hpll_period_detect.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-06-14
-- Last update: 2011-05-11
+-- Last update: 2011-10-29
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
@@ -214,7 +214,7 @@ begin  -- rtl
 -- in FBCR register.
 -------------------------------------------------------------------------------

-  freq_err_output : process(clk_sys_i, rst_n_sysclk_i)
+  freq_err_output : process(clk_sys_i)
  begin
    if rising_edge(clk_sys_i) then
      if rst_n_sysclk_i = '0' then