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White Rabbit core collection
Commit 5947d8b3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_softpll_ng: CRR_IN/CRR_OUT registers (counter sync) added

parent be6a029d
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modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ 5947d8b3
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Mon Apr 16 16:49:35 2012
-- Created : Mon Jul 23 15:02:57 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -115,6 +115,8 @@ begin
spll_deglitch_thr_int <= "0000000000000000";
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
regs_o.crr_in_load_o <= '0';
regs_o.crr_out_load_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -135,6 +137,8 @@ begin
regs_o.dac_main_dac_sel_wr_o <= '0';
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
regs_o.crr_in_load_o <= '0';
regs_o.crr_out_load_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -148,6 +152,8 @@ begin
regs_o.dac_main_dac_sel_wr_o <= '0';
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
regs_o.crr_in_load_o <= '0';
regs_o.crr_out_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -513,6 +519,36 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
regs_o.crr_in_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.crr_in_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
regs_o.crr_out_load_o <= '1';
end if;
rddata_reg(15 downto 0) <= regs_i.crr_out_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
......@@ -827,6 +863,10 @@ begin
-- End-of-Sample
-- pass-through field: End-of-Sample in register: Debug FIFO Register - SPLL side
regs_o.dfr_spll_eos_o <= wrdata_reg(31);
-- Counter Resync
regs_o.crr_in_o <= wrdata_reg(31 downto 0);
-- Counter Resync
regs_o.crr_out_o <= wrdata_reg(15 downto 0);
-- extra code for reg/fifo/mem: Debug FIFO Register - Host side
spll_dfr_host_in_int(31 downto 0) <= regs_i.dfr_host_value_i;
spll_dfr_host_in_int(47 downto 32) <= regs_i.dfr_host_seq_id_i;
......
modules/wr_softpll_ng/spll_wb_slave.wb
View file @ 5947d8b3
......@@ -284,6 +284,40 @@ peripheral {
};
};
reg {
name = "Counter Resync Register - input channels";
prefix = "CRR_IN";
field {
name = "Counter Resync";
description = "write 1: triggers resynchronization of this channel's DDMTD free-running counter with Out Clock 0\
write 0: no effect\
read 1: resync in progress\
read 0: resync done";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Counter Resync Register - output channels";
prefix = "CRR_OUT";
field {
name = "Counter Resync";
description = "write 1: triggers resynchronization of this channel's DDMTD free-running counter with Out Clock 0\
write 0: no effect";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ 5947d8b3
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Mon Apr 16 16:49:35 2012
-- Created : Mon Jul 23 15:02:57 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -31,6 +31,8 @@ package spll_wbgen2_pkg is
ocer_i : std_logic_vector(7 downto 0);
per_hpll_error_i : std_logic_vector(15 downto 0);
per_hpll_valid_i : std_logic;
crr_in_i : std_logic_vector(31 downto 0);
crr_out_i : std_logic_vector(15 downto 0);
dfr_host_wr_req_i : std_logic;
dfr_host_value_i : std_logic_vector(31 downto 0);
dfr_host_seq_id_i : std_logic_vector(15 downto 0);
......@@ -51,6 +53,8 @@ package spll_wbgen2_pkg is
ocer_i => (others => '0'),
per_hpll_error_i => (others => '0'),
per_hpll_valid_i => '0',
crr_in_i => (others => '0'),
crr_out_i => (others => '0'),
dfr_host_wr_req_i => '0',
dfr_host_value_i => (others => '0'),
dfr_host_seq_id_i => (others => '0'),
......@@ -86,6 +90,10 @@ package spll_wbgen2_pkg is
dfr_spll_value_wr_o : std_logic;
dfr_spll_eos_o : std_logic;
dfr_spll_eos_wr_o : std_logic;
crr_in_o : std_logic_vector(31 downto 0);
crr_in_load_o : std_logic;
crr_out_o : std_logic_vector(15 downto 0);
crr_out_load_o : std_logic;
dfr_host_wr_full_o : std_logic;
dfr_host_wr_empty_o : std_logic;
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
......@@ -117,6 +125,10 @@ package spll_wbgen2_pkg is
dfr_spll_value_wr_o => '0',
dfr_spll_eos_o => '0',
dfr_spll_eos_wr_o => '0',
crr_in_o => (others => '0'),
crr_in_load_o => '0',
crr_out_o => (others => '0'),
crr_out_load_o => '0',
dfr_host_wr_full_o => '0',
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
......@@ -162,6 +174,8 @@ tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i);
tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i);
tmp.per_hpll_error_i := f_x_to_zero(left.per_hpll_error_i) or f_x_to_zero(right.per_hpll_error_i);
tmp.per_hpll_valid_i := f_x_to_zero(left.per_hpll_valid_i) or f_x_to_zero(right.per_hpll_valid_i);
tmp.crr_in_i := f_x_to_zero(left.crr_in_i) or f_x_to_zero(right.crr_in_i);
tmp.crr_out_i := f_x_to_zero(left.crr_out_i) or f_x_to_zero(right.crr_out_i);
tmp.dfr_host_wr_req_i := f_x_to_zero(left.dfr_host_wr_req_i) or f_x_to_zero(right.dfr_host_wr_req_i);
tmp.dfr_host_value_i := f_x_to_zero(left.dfr_host_value_i) or f_x_to_zero(right.dfr_host_value_i);
tmp.dfr_host_seq_id_i := f_x_to_zero(left.dfr_host_seq_id_i) or f_x_to_zero(right.dfr_host_seq_id_i);
......
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ 5947d8b3
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2012-04-30
-- Last update: 2012-07-23
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -102,7 +102,7 @@ entity wr_softpll_ng is
g_bb_log2_gating : integer := 10;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
......@@ -125,7 +125,7 @@ entity wr_softpll_ng is
-- g_with_ext_clock_input == true
clk_ext_i : in std_logic;
-- External clock sync/alignment singnal. SoftPLL will clk_ext_i/clk_fb_i(0)
-- External clock sync/alignment singnal. SoftPLL will align clk_ext_i/clk_fb_i(0)
-- to match the edges immediately following the rising edge in sync_p_i.
sync_p_i : in std_logic;
......@@ -199,17 +199,20 @@ architecture rtl of wr_softpll_ng is
component dmtd_with_deglitcher
generic (
g_counter_bits : natural;
g_chipscope : boolean := false;
g_divide_input_by_2 : boolean := false);
g_divide_input_by_2 : boolean);
port (
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_in_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_dmtd_en_i : in std_logic;
clk_sys_i : in std_logic;
resync_p_a_i : in std_logic := '0';
resync_p_o : out std_logic;
resync_start_p_i : in std_logic;
resync_done_o : out std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
clk_dmtd_en_i : in std_logic := '1';
deglitch_threshold_i : in std_logic_vector(15 downto 0);
dbg_dmtdout_o : out std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
......@@ -380,7 +383,11 @@ architecture rtl of wr_softpll_ng is
signal bb_sync_en, bb_sync_done : std_logic;
signal ext_ref_present : std_logic;
signal fb_resync_out : std_logic_vector(g_num_outputs-1 downto 0);
signal ref_resync_start_p : std_logic_vector(31 downto 0);
signal fb_resync_start_p : std_logic_vector(15 downto 0);
begin -- rtl
......@@ -483,7 +490,6 @@ begin -- rtl
DMTD_REF : dmtd_with_deglitcher
generic map (
g_counter_bits => g_tag_bits,
g_chipscope => false,
g_divide_input_by_2 => g_divide_input_by_2)
port map (
rst_n_dmtdclk_i => rst_n_dmtdclk,
......@@ -495,6 +501,11 @@ begin -- rtl
clk_sys_i => clk_sys_i,
clk_in_i => dmtd_ref_clk_in(i),
resync_done_o => regs_out.crr_in_i(i),
resync_start_p_i => ref_resync_start_p(i),
resync_p_a_i => fb_resync_out(0),
resync_p_o => open,
tag_o => tags(i),
tag_stb_p1_o => tags_p(i),
shift_en_i => '0',
......@@ -523,6 +534,11 @@ begin -- rtl
clk_sys_i => clk_sys_i,
clk_in_i => dmtd_fb_clk_in(i),
resync_done_o => regs_out.crr_out_i(i),
resync_start_p_i => fb_resync_start_p(i),
resync_p_a_i => fb_resync_out(0),
resync_p_o => fb_resync_out(i),
tag_o => tags(i+g_num_ref_inputs),
tag_stb_p1_o => tags_p(i+g_num_ref_inputs),
shift_en_i => '0',
......@@ -533,6 +549,7 @@ begin -- rtl
end generate gen_feedback_dmtds;
gen_bb_detector : if(g_with_ext_clock_input) generate
......@@ -632,9 +649,19 @@ begin -- rtl
irq_tag_i => irq_tag);
-- Counter resync logic
process(regs_in)
begin
for i in 0 to g_num_outputs-1 loop
fb_resync_start_p(i) <= regs_in.crr_out_load_o and regs_in.crr_out_o(i);
end loop;
for i in 0 to g_num_ref_inputs-1 loop
ref_resync_start_p(i) <= regs_in.crr_in_load_o and regs_in.crr_in_o(i);
end loop; -- i
end process;
wb_irq_o <= wb_irq_out;
gen_with_period_detector : if(g_with_period_detector) generate
per_clk_ref(g_num_ref_inputs-1 downto 0) <= clk_ref_i; -- and g_period_detector_ref_mask(g_num_ref_inputs-1 downto 0);
......@@ -654,6 +681,7 @@ begin -- rtl
freq_err_stb_p_o => dmtd_freq_err_stb_p,
in_sel_i => regs_in.csr_per_sel_o(4 downto 0));
p_collect_tags_hpll : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -684,13 +712,6 @@ begin -- rtl
end generate gen_without_period_detector;
dac_dmtd_load_o <= regs_in.dac_hpll_wr_o;
dac_dmtd_data_o <= regs_in.dac_hpll_o;
dac_out_data_o <= regs_in.dac_main_value_o;
dac_out_sel_o <= regs_in.dac_main_dac_sel_o;
dac_out_load_o <= regs_in.dac_main_value_wr_o;
p_ocer_rcer_regs : process(clk_sys_i)
begin
......@@ -880,5 +901,11 @@ begin -- rtl
regs_out.csr_n_ref_i <= std_logic_vector(to_unsigned(g_num_ref_inputs, regs_out.csr_n_ref_i'length));
regs_out.csr_n_out_i <= std_logic_vector(to_unsigned(g_num_outputs, regs_out.csr_n_out_i'length));
dac_dmtd_load_o <= regs_in.dac_hpll_wr_o;
dac_dmtd_data_o <= regs_in.dac_hpll_o;
dac_out_data_o <= regs_in.dac_main_value_o;
dac_out_sel_o <= regs_in.dac_main_dac_sel_o;
dac_out_load_o <= regs_in.dac_main_value_wr_o;
end rtl;
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