hdl: move Xilinx UCF files for SPEC and SVEC into the syn/ folder.

This allows to use the same top level vhd for different synthesis targets. Example, we can use the spec_ref_design from top/ in two different syn/, one for a SPEC45T and another one for a SPEC150T.

hdl: move Xilinx UCF files for SPEC and SVEC into the syn/ folder.
This allows to use the same top level vhd for different synthesis targets. Example, we can use the spec_ref_design from top/ in two different syn/, one for a SPEC45T and another one for a SPEC150T.
5d49a112 · Dimitris Lampridis · a5838912 · 5d49a112 · 5d49a112 · 5d49a112
Commit 5d49a112 authored Nov 30, 2018 by Dimitris Lampridis
6 changed files
--- a/syn/spec_ref_design/Manifest.py
+++ b/syn/spec_ref_design/Manifest.py
@@ -11,4 +11,12 @@ syn_project = "spec_wr_ref.xise"

 syn_tool = "ise"

-modules = { "local" : "../../top/spec_ref_design/"}
+files = [
+    "spec_wr_ref_top.ucf",
+]
+
+modules = {
+    "local" : [
+        "../../top/spec_ref_design/",
+    ],
+}
--- a/top/spec_ref_design/spec_wr_ref_top.ucf
+++ b/top/spec_ref_design/spec_wr_ref_top.ucf
--- a/syn/svec_ref_design/Manifest.py
+++ b/syn/svec_ref_design/Manifest.py
@@ -11,8 +11,12 @@ syn_project = "svec_wr_ref.xise"

 syn_tool = "ise"

+files = [
+    "svec_wr_ref_top.ucf",
+]
+
 modules = {
    "local" : [
        "../../top/svec_ref_design/",
-    ]
+    ],
 }
--- a/top/svec_ref_design/svec_wr_ref_top.ucf
+++ b/top/svec_ref_design/svec_wr_ref_top.ucf
--- a/top/spec_ref_design/Manifest.py
+++ b/top/spec_ref_design/Manifest.py
@@ -2,7 +2,6 @@ fetchto = "../../ip_cores"

 files = [
    "spec_wr_ref_top.vhd",
-    "spec_wr_ref_top.ucf",
 ]

 modules = {

--- a/top/svec_ref_design/Manifest.py
+++ b/top/svec_ref_design/Manifest.py
@@ -2,7 +2,6 @@ fetchto = "../../ip_cores"

 files = [
    "svec_wr_ref_top.vhd",
-    "svec_wr_ref_top.ucf",
 ]

 modules = {