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White Rabbit core collection
Commit 5e846093 authored by Maciej Lipinski's avatar Maciej Lipinski
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[board/spec/svec/vfchd] change value of g_dpram_initf from path to 

"default_{xilinx,alter}"
parent 829ec10e
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Showing with 12 additions and 12 deletions
board/spec/wr_spec_pkg.vhd
View file @ 5e846093
......@@ -15,7 +15,7 @@ package wr_spec_pkg is
g_with_external_clock_input : boolean := TRUE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -97,7 +97,7 @@ package wr_spec_pkg is
g_with_external_clock_input : integer := 1;
g_fabric_iface : string := "PLAINFBRC";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_vector_width : integer := 0;
......
board/spec/wrc_board_spec.vhd
View file @ 5e846093
......@@ -66,7 +66,7 @@ entity wrc_board_spec is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......
board/spec/xwrc_board_spec.vhd
View file @ 5e846093
......@@ -67,7 +67,7 @@ entity xwrc_board_spec is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......
board/svec/wr_svec_pkg.vhd
View file @ 5e846093
......@@ -15,7 +15,7 @@ package wr_svec_pkg is
g_with_external_clock_input : boolean := TRUE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -98,7 +98,7 @@ package wr_svec_pkg is
g_with_external_clock_input : integer := 1;
g_fabric_iface : string := "PLAINFBRC";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_vector_width : integer := 0;
......
board/svec/wrc_board_svec.vhd
View file @ 5e846093
......@@ -66,7 +66,7 @@ entity wrc_board_svec is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......
board/svec/xwrc_board_svec.vhd
View file @ 5e846093
......@@ -67,7 +67,7 @@ entity xwrc_board_svec is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......
board/vfchd/wr_vfchd_pkg.vhd
View file @ 5e846093
......@@ -15,7 +15,7 @@ package wr_vfchd_pkg is
g_pcs_16bit : boolean := FALSE;
g_fabric_iface : t_board_fabric_iface := PLAIN;
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif";
g_dpram_initf : string := "default_altera";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -82,7 +82,7 @@ package wr_vfchd_pkg is
g_pcs_16bit : integer := 0;
g_fabric_iface : string := "PLAINFBRC";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif";
g_dpram_initf : string := "default_altera";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_vector_width : integer := 0;
......
board/vfchd/wrc_board_vfchd.vhd
View file @ 5e846093
......@@ -68,7 +68,7 @@ entity wrc_board_vfchd is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif";
g_dpram_initf : string := "default_altera";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......
board/vfchd/xwrc_board_vfchd.vhd
View file @ 5e846093
......@@ -66,7 +66,7 @@ entity xwrc_board_vfchd is
-- data width when g_fabric_iface = "streamers" (otherwise ignored)
g_streamer_width : integer := 32;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif";
g_dpram_initf : string := "default_altera";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......
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