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White Rabbit core collection
Commit 621486b8 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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board: revert system reset output to active low

parent 0d3046df
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Showing with 35 additions and 36 deletions
board/svec/wr_svec_pkg.vhd
View file @ 621486b8
......@@ -24,7 +24,7 @@ package wr_svec_pkg is
clk_10m_ext_ref_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
......@@ -101,7 +101,7 @@ package wr_svec_pkg is
clk_10m_ext_ref_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
......
board/svec/wrc_board_svec.vhd
View file @ 621486b8
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-02-16
-- Last update: 2017-02-17
-- Last update: 2017-02-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -93,8 +93,8 @@ entity wrc_board_svec is
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- active high reset output, synchronous to clk_sys_62m5_o
rst_sys_62m5_o : out std_logic;
-- active low reset output, synchronous to clk_sys_62m5_o
rst_sys_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
......@@ -340,7 +340,7 @@ begin -- architecture struct
clk_10m_ext_ref_i => clk_10m_ext_ref_i,
clk_sys_62m5_o => clk_sys_62m5_o,
clk_ref_125m_o => clk_ref_125m_o,
rst_sys_62m5_o => rst_sys_62m5_o,
rst_sys_62m5_n_o => rst_sys_62m5_n_o,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
......
board/svec/xwrc_board_svec.vhd
View file @ 621486b8
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-02-17
-- Last update: 2017-02-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -94,8 +94,8 @@ entity xwrc_board_svec is
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- active high reset output, synchronous to clk_sys_62m5_o
rst_sys_62m5_o : out std_logic;
-- active low reset output, synchronous to clk_sys_62m5_o
rst_sys_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
......@@ -384,7 +384,7 @@ begin -- architecture struct
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0);
rst_sys_62m5_o <= not rst_62m5_n;
rst_sys_62m5_n_o <= rst_62m5_n;
-----------------------------------------------------------------------------
-- 2x SPI DAC
......
board/vfchd/wr_vfchd_pkg.vhd
View file @ 621486b8
......@@ -22,7 +22,7 @@ package wr_vfchd_pkg is
areset_n_i : in std_logic;
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
dac_ref_sync_n_o : out std_logic;
dac_dmtd_sync_n_o : out std_logic;
dac_din_o : out std_logic;
......@@ -83,7 +83,7 @@ package wr_vfchd_pkg is
areset_n_i : in std_logic;
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
dac_ref_sync_n_o : out std_logic;
dac_dmtd_sync_n_o : out std_logic;
dac_din_o : out std_logic;
......
board/vfchd/wrc_board_vfchd.vhd
View file @ 621486b8
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-02-16
-- Last update: 2017-02-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -90,8 +90,8 @@ entity wrc_board_vfchd is
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- active high reset output, synchronous to clk_sys_62m5_o
rst_sys_62m5_o : out std_logic;
-- active low reset output, synchronous to clk_sys_62m5_o
rst_sys_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
......@@ -316,7 +316,7 @@ begin -- architecture struct
areset_n_i => areset_n_i,
clk_sys_62m5_o => clk_sys_62m5_o,
clk_ref_125m_o => clk_ref_125m_o,
rst_sys_62m5_o => rst_sys_62m5_o,
rst_sys_62m5_n_o => rst_sys_62m5_n_o,
dac_ref_sync_n_o => dac_ref_sync_n_o,
dac_dmtd_sync_n_o => dac_dmtd_sync_n_o,
dac_din_o => dac_din_o,
......
board/vfchd/xwrc_board_vfchd.vhd
View file @ 621486b8
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-02-16
-- Last update: 2017-02-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -88,8 +88,8 @@ entity xwrc_board_vfchd is
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- active high reset output, synchronous to clk_sys_62m5_o
rst_sys_62m5_o : out std_logic;
-- active low reset output, synchronous to clk_sys_62m5_o
rst_sys_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
......@@ -329,7 +329,7 @@ begin -- architecture struct
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0);
rst_sys_62m5_o <= not rst_62m5_n;
rst_sys_62m5_n_o <= rst_62m5_n;
-----------------------------------------------------------------------------
-- SPI DAC (2-channel)
......
top/svec_ref_design/svec_wr_ref_top.vhd
View file @ 621486b8
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-02-17
-- Last update: 2017-02-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SVEC.
......@@ -227,7 +227,6 @@ architecture top of svec_wr_ref_top is
-- clock and reset
signal areset_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
......@@ -274,9 +273,6 @@ begin -- architecture top
-- logic AND of all async reset sources (active low)
areset_n <= vme_sysreset_n_i and rst_n_i;
-- System clock reset (active low)
rst_sys_62m5_n <= not rst_sys_62m5;
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar
-----------------------------------------------------------------------------
......@@ -362,7 +358,7 @@ begin -- architecture top
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_o => rst_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
......
top/vfchd_ref_design/vfchd_wr_ref_top.vhd
View file @ 621486b8
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-01-24
-- Last update: 2017-02-17
-- Last update: 2017-02-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the VFC-HD.
......@@ -250,10 +250,11 @@ architecture top of vfchd_wr_ref_top is
signal cnx2_slave_in : t_wishbone_slave_in_array(c_NUM_WB2_SLAVES-1 downto 0);
-- clock and reset
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
......@@ -317,6 +318,8 @@ architecture top of vfchd_wr_ref_top is
begin -- architecture top
rst_sys_62m5 <= not rst_sys_62m5_n;
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar
-----------------------------------------------------------------------------
......@@ -331,7 +334,7 @@ begin -- architecture top
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => not rst_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx1_master_out,
slave_o => cnx1_master_in,
master_i => cnx1_slave_out,
......@@ -344,7 +347,7 @@ begin -- architecture top
cmp_vme_core : xvme64x_core
port map (
clk_i => clk_sys_62m5,
rst_n_i => not rst_sys_62m5,
rst_n_i => rst_sys_62m5_n,
VME_AS_n_i => vme_as_n_i,
VME_RST_n_i => io_exp_init_done,
VME_WRITE_n_i => vme_write_n_i,
......@@ -400,7 +403,7 @@ begin -- architecture top
areset_n_i => areset_n_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_o => rst_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
dac_ref_sync_n_o => dac_ref_sync_n_o,
dac_dmtd_sync_n_o => dac_dmtd_sync_n_o,
dac_din_o => dac_din_o,
......@@ -453,7 +456,7 @@ begin -- architecture top
g_mask => (0 => (others => '0')))
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => not rst_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx2_master_out,
slave_o => cnx2_master_in,
master_i => cnx2_slave_out,
......@@ -664,7 +667,7 @@ begin -- architecture top
g_width => 5000000)
port map (
clk_i => clk_sys_62m5,
rst_n_i => not rst_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => pps_led,
extended_o => pps_led_d);
......
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