Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
67753a99
Commit
67753a99
authored
May 11, 2011
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
removed wrc_core (belongs to another repo)
parent
2872de8b
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
8 changed files
with
0 additions
and
1994 deletions
+0
-1994
Manifest.py
Manifest.py
+0
-1
Manifest.py
modules/wrc_core/Manifest.py
+0
-6
wb_reset.vhd
modules/wrc_core/wb_reset.vhd
+0
-88
wr_core.vhd
modules/wrc_core/wr_core.vhd
+0
-886
wrc_dpram.vhd
modules/wrc_core/wrc_dpram.vhd
+0
-119
wrc_dumb_rx_packet_filter.vhd
modules/wrc_core/wrc_dumb_rx_packet_filter.vhd
+0
-232
wrc_periph.vhd
modules/wrc_core/wrc_periph.vhd
+0
-290
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+0
-372
No files found.
Manifest.py
View file @
67753a99
...
...
@@ -4,7 +4,6 @@ modules = {"local" :
"modules/wr_mini_nic"
,
"modules/wr_softpll"
,
"modules/wrc_lm32"
,
"modules/wrc_core"
,
"modules/wrsw_endpoint"
,
"modules/wrsw_pps_gen"
]}
\ No newline at end of file
modules/wrc_core/Manifest.py
deleted
100644 → 0
View file @
2872de8b
files
=
[
"wr_core.vhd"
,
"wrc_dpram.vhd"
,
"wrcore_pkg.vhd"
,
"wrc_periph.vhd"
,
"wb_reset.vhd"
,
"wrc_dumb_rx_packet_filter.vhd"
];
modules/wrc_core/wb_reset.vhd
deleted
100644 → 0
View file @
2872de8b
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core ZPU reset generator
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_reset.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 2011-04-04
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WB_RESET is a reset signal generator for ZPU. It is controlled by wishbone
-- and is used by ZPU firmware loader(zpu-loader) to reset the processor during
-- copying the binary to dpram.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-04 1.0 greg.d Created
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
wb_reset
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
genrst_n_o
:
out
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
wb_reset
;
architecture
behaviour
of
wb_reset
is
constant
c_RST_REG
:
std_logic_vector
(
1
downto
0
)
:
=
"00"
;
signal
rst_reg
:
std_logic_vector
(
7
downto
0
);
signal
grst_n
:
std_logic
;
begin
process
(
clk_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
wb_ack_o
<=
'0'
;
rst_reg
<=
(
others
=>
'0'
);
elsif
(
rising_edge
(
clk_i
)
)
then
if
(
wb_stb_i
=
'1'
and
wb_cyc_i
=
'1'
and
wb_we_i
=
'1'
)
then
case
wb_addr_i
is
when
c_RST_REG
=>
rst_reg
<=
wb_data_i
(
7
downto
0
);
when
others
=>
end
case
;
wb_ack_o
<=
'1'
;
else
wb_ack_o
<=
'0'
;
end
if
;
end
if
;
end
process
;
process
(
clk_i
,
rst_n_i
)
variable
cnt
:
integer
range
1
to
5
;
begin
if
(
rst_n_i
=
'0'
)
then
grst_n
<=
'1'
;
elsif
(
rising_edge
(
clk_i
)
)
then
if
(
rst_reg
(
0
)
=
'1'
)
then
grst_n
<=
'0'
;
else
grst_n
<=
'1'
;
end
if
;
end
if
;
end
process
;
genrst_n_o
<=
grst_n
;
end
behaviour
;
modules/wrc_core/wr_core.vhd
deleted
100644 → 0
View file @
2872de8b
This diff is collapsed.
Click to expand it.
modules/wrc_core/wrc_dpram.vhd
deleted
100644 → 0
View file @
2872de8b
-------------------------------------------------------------------------------
-- Title : Dual-port RAM for WR core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrc_dpram.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-15
-- Last update: 2011-05-11
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Dual port RAM from genrams with wishbone interface
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-15 1.0 greg.d Created
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
work
;
use
work
.
genram_pkg
.
all
;
entity
wrc_dpram
is
generic
(
g_data_width
:
natural
:
=
32
;
g_size
:
natural
:
=
16384
;
-- 16 * 32bit = 64kB
g_with_byte_enable
:
boolean
:
=
true
;
g_addr_conflict_resolution
:
string
:
=
"read_first"
;
g_init_file
:
string
:
=
""
;
g_dual_clock
:
boolean
:
=
false
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
--PORT A (Wishbone)
wb_addr_i
:
in
std_logic_vector
(
f_log2_size
(
g_size
)
-1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
g_data_width
-1
downto
0
);
wb_data_o
:
out
std_logic_vector
(
g_data_width
-1
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
g_data_width
/
8-1
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
--PORT B (miniNIC)
mem_addr_i
:
in
std_logic_vector
(
f_log2_size
(
g_size
)
-1
downto
0
);
mem_data_i
:
in
std_logic_vector
(
31
downto
0
);
mem_data_o
:
out
std_logic_vector
(
31
downto
0
);
mem_wr_i
:
in
std_logic
);
end
wrc_dpram
;
architecture
struct
of
wrc_dpram
is
signal
s_wb_ack_o
:
std_logic
;
signal
muxed_we
:
std_logic
;
signal
s_bwea
:
std_logic_vector
(
3
downto
0
);
signal
s_bweb
:
std_logic_vector
(
3
downto
0
);
begin
wb_ack_o
<=
s_wb_ack_o
;
DPRAM
:
generic_dpram
generic
map
(
-- standard parameters
g_data_width
=>
g_data_width
,
g_size
=>
g_size
,
g_with_byte_enable
=>
g_with_byte_enable
,
g_addr_conflict_resolution
=>
g_addr_conflict_resolution
,
-- g_init_file => g_init_file,
g_dual_clock
=>
g_dual_clock
)
port
map
(
rst_n_i
=>
rst_n_i
,
-- Port A
clka_i
=>
clk_i
,
bwea_i
=>
s_bwea
,
wea_i
=>
muxed_we
,
--wb_we_i,
aa_i
=>
wb_addr_i
,
da_i
=>
wb_data_i
,
qa_o
=>
wb_data_o
,
-- Port B
clkb_i
=>
clk_i
,
bweb_i
=>
s_bweb
,
web_i
=>
mem_wr_i
,
ab_i
=>
mem_addr_i
,
db_i
=>
mem_data_i
,
qb_o
=>
mem_data_o
);
s_bwea
<=
wb_sel_i
when
(
wb_we_i
=
'1'
and
wb_stb_i
=
'1'
and
wb_cyc_i
=
'1'
)
else
"0000"
;
s_bweb
<=
(
others
=>
mem_wr_i
);
-- muxed_we <= wb_we_i when (wb_stb_i='1' and wb_cyc_i='1') else '0';
process
(
clk_i
)
begin
if
(
rising_edge
(
clk_i
))
then
if
(
rst_n_i
=
'0'
)
then
s_wb_ack_o
<=
'0'
;
else
if
(
s_wb_ack_o
=
'1'
)
then
s_wb_ack_o
<=
'0'
;
else
s_wb_ack_o
<=
wb_cyc_i
and
wb_stb_i
;
end
if
;
end
if
;
end
if
;
end
process
;
end
struct
;
modules/wrc_core/wrc_dumb_rx_packet_filter.vhd
deleted
100644 → 0
View file @
2872de8b
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
work
;
use
work
.
endpoint_pkg
.
all
;
entity
wrc_dumb_rx_packet_filter
is
generic
(
g_match_etype0
:
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
g_match_etype1
:
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
g_match_etype2
:
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
g_match_etype3
:
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
src_cyc_o
:
out
std_logic
;
src_stb_o
:
out
std_logic
;
src_we_o
:
out
std_logic
;
src_stall_i
:
in
std_logic
;
src_ack_i
:
in
std_logic
;
snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
snk_cyc_i
:
in
std_logic
;
snk_stb_i
:
in
std_logic
;
snk_we_i
:
in
std_logic
;
snk_stall_o
:
out
std_logic
;
snk_ack_o
:
out
std_logic
);
end
wrc_dumb_rx_packet_filter
;
architecture
behavioral
of
wrc_dumb_rx_packet_filter
is
type
t_wrf_xfer
is
record
d
:
std_logic_vector
(
15
downto
0
);
a
:
std_logic_vector
(
1
downto
0
);
sel
:
std_logic_vector
(
1
downto
0
);
end_cycle
:
std_logic
;
valid
:
std_logic
;
end
record
;
constant
c_sreg_size
:
integer
:
=
8
;
type
t_wrf_sreg
is
array
(
c_sreg_size
-1
downto
0
)
of
t_wrf_xfer
;
signal
sreg
:
t_wrf_sreg
;
signal
ethertype_counter
:
unsigned
(
9
downto
0
);
type
t_state
is
(
S_WAIT_CYCLE
,
S_DATA
,
S_TERM_CYCLE
,
S_WAIT_ACKS
);
signal
state
:
t_state
;
signal
stall_src
:
std_logic
;
signal
ack_counter
:
unsigned
(
3
downto
0
);
signal
src_stb_int
:
std_logic
;
signal
src_cyc_int
:
std_logic
;
function
f_classify_etype
(
etype
:
std_logic_vector
)
return
std_logic_vector
is
begin
if
(
etype
=
g_match_etype0
)
then
return
"00000001"
;
end
if
;
if
(
etype
=
g_match_etype1
)
then
return
"00000010"
;
end
if
;
if
(
etype
=
g_match_etype2
)
then
return
"00000100"
;
end
if
;
if
(
etype
=
g_match_etype3
)
then
return
"00001000"
;
end
if
;
return
"00000000"
;
end
function
;
begin
-- behavioral
snk_stall_o
<=
src_stall_i
or
stall_src
;
process
(
clk_sys_i
)
variable
tmp
:
t_wrf_status_reg
;
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
)
then
for
i
in
0
to
7
loop
sreg
(
i
)
.
end_cycle
<=
'0'
;
end
loop
;
-- i in 0 to 7
ethertype_counter
<=
to_unsigned
(
1
,
ethertype_counter
'length
);
snk_ack_o
<=
'0'
;
src_cyc_int
<=
'0'
;
src_stb_int
<=
'0'
;
stall_src
<=
'0'
;
src_dat_o
<=
(
others
=>
'0'
);
src_sel_o
<=
(
others
=>
'0'
);
src_adr_o
<=
(
others
=>
'0'
);
else
if
(
src_cyc_int
=
'0'
)
then
ack_counter
<=
(
others
=>
'0'
);
else
if
(
src_stb_int
=
'1'
and
src_ack_i
=
'0'
)
then
ack_counter
<=
ack_counter
+
1
;
elsif
(
src_stb_int
=
'0'
and
src_ack_i
=
'1'
)
then
ack_counter
<=
ack_counter
-
1
;
end
if
;
end
if
;
case
state
is
when
S_WAIT_CYCLE
=>
stall_src
<=
'0'
;
if
(
snk_cyc_i
=
'1'
)
then
-- beginning of a new frame
if
(
snk_stb_i
=
'1'
)
then
sreg
(
0
)
.
a
<=
snk_adr_i
;
sreg
(
0
)
.
d
<=
snk_dat_i
;
sreg
(
0
)
.
sel
<=
snk_sel_i
;
sreg
(
0
)
.
end_cycle
<=
'0'
;
sreg
(
0
)
.
valid
<=
'1'
;
sreg
(
c_sreg_size
-1
downto
1
)
<=
sreg
(
c_sreg_size
-2
downto
0
);
if
(
snk_adr_i
=
c_WRF_DATA
)
then
ethertype_counter
<=
ethertype_counter
sll
1
;
end
if
;
snk_ack_o
<=
'1'
;
state
<=
S_DATA
;
else
stall_src
<=
'0'
;
snk_ack_o
<=
'0'
;
ethertype_counter
<=
to_unsigned
(
1
,
ethertype_counter
'length
);
end
if
;
src_cyc_int
<=
'1'
;
else
for
i
in
0
to
7
loop
sreg
(
i
)
.
end_cycle
<=
'0'
;
sreg
(
i
)
.
valid
<=
'0'
;
end
loop
;
-- i in 0 to 7
src_cyc_int
<=
'0'
;
end
if
;
when
S_DATA
=>
if
(
snk_cyc_i
=
'0'
)
then
state
<=
S_TERM_CYCLE
;
stall_src
<=
'1'
;
sreg
(
0
)
.
end_cycle
<=
'1'
;
-- sreg(0).valid <= '0';
-- sreg(c_sreg_size-1 downto 1) <= sreg(c_sreg_size-1-1 downto 0);
elsif
(
snk_stb_i
=
'1'
)
then
sreg
(
0
)
.
a
<=
snk_adr_i
;
sreg
(
0
)
.
d
<=
snk_dat_i
;
sreg
(
0
)
.
sel
<=
snk_sel_i
;
sreg
(
0
)
.
end_cycle
<=
'0'
;
sreg
(
0
)
.
valid
<=
'1'
;
sreg
(
c_sreg_size
-1
downto
1
)
<=
sreg
(
c_sreg_size
-1-1
downto
0
);
if
(
ethertype_counter
(
6
)
=
'1'
)
then
tmp
.
match_class
:
=
f_classify_etype
(
snk_dat_i
);
tmp
.
rx_error
:
=
'0'
;
tmp
.
is_hp
:
=
'0'
;
sreg
(
7
)
.
valid
<=
'1'
;
sreg
(
7
)
.
a
<=
c_WRF_STATUS
;
sreg
(
7
)
.
d
<=
f_marshall_wrf_status
(
tmp
);
sreg
(
7
)
.
end_cycle
<=
'0'
;
sreg
(
7
)
.
sel
<=
"11"
;
end
if
;
src_stb_int
<=
sreg
(
c_sreg_size
-1
)
.
valid
;
src_dat_o
<=
sreg
(
c_sreg_size
-1
)
.
d
;
src_adr_o
<=
sreg
(
c_sreg_size
-1
)
.
a
;
src_sel_o
<=
sreg
(
c_sreg_size
-1
)
.
sel
;
if
(
snk_adr_i
=
c_WRF_DATA
)
then
ethertype_counter
<=
ethertype_counter
sll
1
;
end
if
;
snk_ack_o
<=
'1'
;
else
src_stb_int
<=
'0'
;
snk_ack_o
<=
'0'
;
end
if
;
when
S_TERM_CYCLE
=>
if
(
src_stall_i
=
'0'
)
then
if
(
sreg
(
c_sreg_size
-1
)
.
end_cycle
=
'1'
)
then
state
<=
S_WAIT_ACKS
;
end
if
;
src_dat_o
<=
sreg
(
c_sreg_size
-1
)
.
d
;
src_adr_o
<=
sreg
(
c_sreg_size
-1
)
.
a
;
src_sel_o
<=
sreg
(
c_sreg_size
-1
)
.
sel
;
src_stb_int
<=
sreg
(
c_sreg_size
-1
)
.
valid
;
sreg
(
c_sreg_size
-1
downto
1
)
<=
sreg
(
c_sreg_size
-1-1
downto
0
);
else
src_stb_int
<=
'0'
;
end
if
;
when
S_WAIT_ACKS
=>
src_stb_int
<=
'0'
;
if
(
ack_counter
=
0
)
then
src_cyc_int
<=
'0'
;
state
<=
S_WAIT_CYCLE
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
src_cyc_o
<=
src_cyc_int
;
src_stb_o
<=
src_stb_int
;
src_we_o
<=
'1'
;
end
behavioral
;
modules/wrc_core/wrc_periph.vhd
deleted
100644 → 0
View file @
2872de8b
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core peripherials
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrc_periph.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 2011-04-13
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WRC_PERIPH is a single WB slave which includes all 'small' WB peripherials
-- needed for WR PTP Core. It has: wb_gpio_port, wb_simple_uart, wb_tics and
-- wb_reset.
-- All those modules share Wishbone Slave interface, and the address bus is
-- used to choose one of them at a time.
--
-- wb_addr_i(11:0):
-- (11) -> select wb_reset
-- (10) -> select wb_tics
-- (9) -> select wb_uart
-- (8) -> select wb_gpio
-- (7:0)-> address shared between wb modules inside wrc_periph
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-04 1.0 greg.d Created
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
work
;
use
work
.
wrcore_pkg
.
all
;
entity
wrc_periph
is
generic
(
g_gpio_pins
:
natural
:
=
8
;
g_virtual_uart
:
natural
:
=
0
;
g_tics_period
:
integer
);
port
(
clk_sys_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
gpio_o
:
out
std_logic_vector
(
g_gpio_pins
-1
downto
0
);
gpio_i
:
in
std_logic_vector
(
g_gpio_pins
-1
downto
0
);
gpio_dir_o
:
out
std_logic_vector
(
g_gpio_pins
-1
downto
0
);
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
genrst_n_o
:
out
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
11
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
wrc_periph
;
architecture
struct
of
wrc_periph
is
component
wb_tics
generic
(
g_period
:
integer
);
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
component
;
component
wb_reset
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
genrst_n_o
:
out
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
component
;
component
wb_simple_uart
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
);
end
component
;
component
wb_virtual_uart
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
component
;
component
wb_gpio_port
generic
(
g_num_pins
:
natural
);
port
(
sys_rst_n_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_ack_o
:
out
std_logic
;
gpio_b
:
inout
std_logic_vector
(
g_num_pins
-1
downto
0
));
end
component
;
component
wb_gpio_port_notristates
generic
(
g_num_pins
:
natural
);
port
(
sys_rst_n_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_ack_o
:
out
std_logic
;
gpio_o
:
out
std_logic_vector
(
g_num_pins
-1
downto
0
);
gpio_i
:
in
std_logic_vector
(
g_num_pins
-1
downto
0
);
gpio_dir_o
:
out
std_logic_vector
(
g_num_pins
-1
downto
0
));
end
component
;
type
t_wbdata
is
array
(
3
downto
0
)
of
std_logic_vector
(
31
downto
0
);
signal
wb_cycs_i
:
std_logic_vector
(
3
downto
0
);
signal
wb_stbs_i
:
std_logic_vector
(
3
downto
0
);
signal
wb_acks_o
:
std_logic_vector
(
3
downto
0
);
signal
wb_dats_o
:
t_wbdata
;
begin
GENWB
:
for
I
in
0
to
3
generate
wb_cycs_i
(
I
)
<=
wb_cyc_i
and
wb_addr_i
(
8
+
I
);
wb_stbs_i
(
I
)
<=
wb_stb_i
and
wb_addr_i
(
8
+
I
);
end
generate
;
wb_ack_o
<=
wb_acks_o
(
0
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0001"
)
else
wb_acks_o
(
1
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0010"
)
else
wb_acks_o
(
2
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0100"
)
else
wb_acks_o
(
3
)
when
(
wb_addr_i
(
11
downto
8
)
=
"1000"
)
else
'0'
;
wb_data_o
<=
wb_dats_o
(
0
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0001"
)
else
wb_dats_o
(
1
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0010"
)
else
wb_dats_o
(
2
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0100"
)
else
wb_dats_o
(
3
)
when
(
wb_addr_i
(
11
downto
8
)
=
"1000"
)
else
(
others
=>
'0'
);
GPIO
:
wb_gpio_port_notristates
generic
map
(
g_num_pins
=>
g_gpio_pins
)
port
map
(
sys_rst_n_i
=>
rst_n_i
,
wb_clk_i
=>
clk_sys_i
,
wb_sel_i
=>
wb_sel_i
(
0
),
wb_cyc_i
=>
wb_cycs_i
(
0
),
wb_stb_i
=>
wb_stbs_i
(
0
),
wb_we_i
=>
wb_we_i
,
wb_addr_i
=>
wb_addr_i
(
2
downto
0
),
wb_data_i
=>
wb_data_i
,
wb_data_o
=>
wb_dats_o
(
0
),
wb_ack_o
=>
wb_acks_o
(
0
),
gpio_o
=>
gpio_o
,
gpio_i
=>
gpio_i
,
gpio_dir_o
=>
gpio_dir_o
);
GEN_UART
:
if
(
g_virtual_uart
=
0
)
generate
UART
:
wb_simple_uart
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
wb_addr_i
=>
wb_addr_i
(
1
downto
0
),
wb_data_i
=>
wb_data_i
,
wb_data_o
=>
wb_dats_o
(
1
),
wb_cyc_i
=>
wb_cycs_i
(
1
),
wb_sel_i
=>
wb_sel_i
,
wb_stb_i
=>
wb_stbs_i
(
1
),
wb_we_i
=>
wb_we_i
,
wb_ack_o
=>
wb_acks_o
(
1
),
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
);
end
generate
;
GEN_VIRTUART
:
if
(
g_virtual_uart
=
1
)
generate
VIRTUAL_UART
:
wb_virtual_uart
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_sys_i
,
wb_addr_i
=>
wb_addr_i
(
2
downto
0
),
wb_data_i
=>
wb_data_i
,
wb_data_o
=>
wb_dats_o
(
1
),
wb_cyc_i
=>
wb_cycs_i
(
1
),
wb_sel_i
=>
wb_sel_i
,
wb_stb_i
=>
wb_stbs_i
(
1
),
wb_we_i
=>
wb_we_i
,
wb_ack_o
=>
wb_acks_o
(
1
)
);
end
generate
;
TICS
:
wb_tics
generic
map
(
g_period
=>
g_tics_period
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
wb_addr_i
=>
wb_addr_i
(
1
downto
0
),
wb_data_i
=>
wb_data_i
,
wb_data_o
=>
wb_dats_o
(
2
),
wb_cyc_i
=>
wb_cycs_i
(
2
),
wb_sel_i
=>
wb_sel_i
,
wb_stb_i
=>
wb_stbs_i
(
2
),
wb_we_i
=>
wb_we_i
,
wb_ack_o
=>
wb_acks_o
(
2
)
);
RST_GEN
:
wb_reset
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
genrst_n_o
=>
genrst_n_o
,
wb_addr_i
=>
wb_addr_i
(
1
downto
0
),
wb_data_i
=>
wb_data_i
,
wb_data_o
=>
wb_dats_o
(
3
),
wb_sel_i
=>
wb_sel_i
,
wb_stb_i
=>
wb_stbs_i
(
3
),
wb_cyc_i
=>
wb_cycs_i
(
3
),
wb_we_i
=>
wb_we_i
,
wb_ack_o
=>
wb_acks_o
(
3
)
);
end
struct
;
modules/wrc_core/wrcore_pkg.vhd
deleted
100644 → 0
View file @
2872de8b
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment