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White Rabbit core collection
Commit 67892968 authored by Pascal Bos's avatar Pascal Bos
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Initial commit 


changed pci_rst_n to perst_n, linked to wrc.bin

linked to wrc.bin

linked to wrc.bin

corrected .bram file

corrected .bram file

corrected .bram file
parent f5f7f210
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Showing with 731 additions and 13 deletions
board/spec7/wr_spec7_pkg.vhd
View file @ 67892968
......@@ -110,6 +110,8 @@ package wr_spec7_pkg is
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
......@@ -152,6 +154,152 @@ package wr_spec7_pkg is
link_ok_o : out std_logic);
end component xwrc_board_spec7;
type t_axis_32 is record
data : std_logic_vector(31 DOWNTO 0);
last : std_logic;
valid : std_logic;
ready : std_logic;
keep : std_logic_vector(31/8 DOWNTO 0);
end record t_axis_32;
type t_axis_64 is record
data : std_logic_vector(63 DOWNTO 0);
last : std_logic;
valid : std_logic;
ready : std_logic;
keep : std_logic_vector(63/8 DOWNTO 0);
end record t_axis_64;
-- AXI4-Lite interface, master output ports, 32 bits
type t_axi4_lite_master_out_32 is record
ARVALID : std_logic;
AWVALID : std_logic;
BREADY : std_logic;
RREADY : std_logic;
WLAST : std_logic;
WVALID : std_logic;
ARADDR : std_logic_vector (31 downto 0);
AWADDR : std_logic_vector (31 downto 0);
WDATA : std_logic_vector (31 downto 0);
WSTRB : std_logic_vector (3 downto 0);
end record;
subtype t_axi4_lite_slave_in_32 is t_axi4_lite_master_out_32;
-- AXI4-Lite interface, master input ports, 32 bits
type t_axi4_lite_master_in_32 is record
ARREADY : std_logic;
AWREADY : std_logic;
BVALID : std_logic;
RLAST : std_logic;
RVALID : std_logic;
WREADY : std_logic;
BRESP : std_logic_vector (1 downto 0);
RRESP : std_logic_vector (1 downto 0);
RDATA : std_logic_vector (31 downto 0);
end record;
subtype t_axi4_lite_slave_out_32 is t_axi4_lite_master_in_32;
COMPONENT xdma_0
PORT (
sys_clk : IN STD_LOGIC;
sys_rst_n : IN STD_LOGIC;
user_lnk_up : OUT STD_LOGIC;
pci_exp_txp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pci_exp_txn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pci_exp_rxp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
pci_exp_rxn : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_aclk : OUT STD_LOGIC;
axi_aresetn : OUT STD_LOGIC;
usr_irq_req : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
usr_irq_ack : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axil_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axil_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axil_awvalid : OUT STD_LOGIC;
m_axil_awready : IN STD_LOGIC;
m_axil_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axil_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axil_wvalid : OUT STD_LOGIC;
m_axil_wready : IN STD_LOGIC;
m_axil_bvalid : IN STD_LOGIC;
m_axil_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axil_bready : OUT STD_LOGIC;
m_axil_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axil_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axil_arvalid : OUT STD_LOGIC;
m_axil_arready : IN STD_LOGIC;
m_axil_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axil_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axil_rvalid : IN STD_LOGIC;
m_axil_rready : OUT STD_LOGIC;
s_axis_c2h_tdata_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c2h_tlast_0 : IN STD_LOGIC;
s_axis_c2h_tvalid_0 : IN STD_LOGIC;
s_axis_c2h_tready_0 : OUT STD_LOGIC;
s_axis_c2h_tkeep_0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_h2c_tdata_0 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_h2c_tlast_0 : OUT STD_LOGIC;
m_axis_h2c_tvalid_0 : OUT STD_LOGIC;
m_axis_h2c_tready_0 : IN STD_LOGIC;
m_axis_h2c_tkeep_0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
component Pcie_wrapper is
port (
aclk1_0 : in STD_LOGIC;
pcie_clk : in STD_LOGIC;
pcie_rst_n : in STD_LOGIC;
user_lnk_up_0 : out STD_LOGIC;
usr_irq_ack_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
usr_irq_req_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_0_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_0_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_awvalid : out STD_LOGIC;
M00_AXI_0_awready : in STD_LOGIC;
M00_AXI_0_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_wlast : out STD_LOGIC;
M00_AXI_0_wvalid : out STD_LOGIC;
M00_AXI_0_wready : in STD_LOGIC;
M00_AXI_0_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_bvalid : in STD_LOGIC;
M00_AXI_0_bready : out STD_LOGIC;
M00_AXI_0_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_0_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_0_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_arvalid : out STD_LOGIC;
M00_AXI_0_arready : in STD_LOGIC;
M00_AXI_0_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_rlast : in STD_LOGIC;
M00_AXI_0_rvalid : in STD_LOGIC;
M00_AXI_0_rready : out STD_LOGIC;
pcie_mgt_0_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
pcie_mgt_0_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
pcie_mgt_0_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
pcie_mgt_0_txp : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component Pcie_wrapper;
component xwb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
axi4_slave_i : in t_axi4_lite_slave_in_32;
axi4_slave_o : out t_axi4_lite_slave_out_32;
wb_master_o : out t_wishbone_master_out;
wb_master_i : in t_wishbone_master_in
);
end component;
-- component wrc_board_spec7 is
-- generic (
......
board/spec7/xwrc_board_spec7.vhd
View file @ 67892968
......@@ -175,9 +175,10 @@ entity xwrc_board_spec7 is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- No External WB interface
--External WB interface
---------------------------------------------------------------------------
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
......@@ -358,6 +359,7 @@ begin -- architecture struct
-- The AD9516 on the SPEC7 needs to be initialized before it outputs
-- clk_125m_gtx_p/n_i (which is
cmp_bufgmux: BUFGMUX
port map (
O => clk_sys_62m5,
......@@ -529,6 +531,8 @@ begin -- architecture struct
owr_pwren_o => open,
owr_en_o => onewire_en,
owr_i => onewire_in,
wb_slave_i => wb_slave_i,
wb_slave_o => wb_slave_o,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
......
platform/xilinx/Manifest.py
View file @ 67892968
files = [ "wr_xilinx_pkg.vhd", "xwrc_platform_xilinx.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
modules = {"local" : ["wr_gtp_phy", "chipscope", "wr_pcie"]}
platform/xilinx/wr_pcie/Manifest.py 0 → 100644
View file @ 67892968
files = [ "Pcie.tcl", "wb_axi4lite_bridge.vhd" ]
platform/xilinx/wr_pcie/Pcie.tcl 0 → 100644
View file @ 67892968
################################################################
# This is a generated script based on design: Pcie
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
# I "hacked" this, for the sake of compatability, Vivado gives a warning during synthesis if a different version really doesn't work.
set current_vivado_version [version -short]
set scripts_vivado_version $current_vivado_version
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source Pcie_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7z030fbg676-1
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name Pcie
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:smartconnect:1.0\
xilinx.com:ip:xdma:4.1\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M00_AXI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI_0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {62500000} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4} \
] $M00_AXI_0
set pcie_mgt_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_mgt_0 ]
# Create ports
set aclk1_0 [ create_bd_port -dir I -type clk -freq_hz 62500000 aclk1_0 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {M00_AXI_0} \
] $aclk1_0
set pcie_clk [ create_bd_port -dir I -type clk pcie_clk ]
set pcie_rst_n [ create_bd_port -dir I -type rst pcie_rst_n ]
set user_lnk_up_0 [ create_bd_port -dir O user_lnk_up_0 ]
set usr_irq_ack_0 [ create_bd_port -dir O -from 0 -to 0 usr_irq_ack_0 ]
set usr_irq_req_0 [ create_bd_port -dir I -from 0 -to 0 usr_irq_req_0 ]
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_CLKS {2} \
CONFIG.NUM_SI {1} \
] $smartconnect_0
# Create instance: xdma_0, and set properties
set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
set_property -dict [ list \
CONFIG.PF0_DEVICE_ID_mqdma {9022} \
CONFIG.PF2_DEVICE_ID_mqdma {9022} \
CONFIG.PF3_DEVICE_ID_mqdma {9022} \
CONFIG.axilite_master_en {true} \
CONFIG.axilite_master_scale {Kilobytes} \
CONFIG.axilite_master_size {256} \
CONFIG.axisten_freq {125} \
CONFIG.cfg_mgmt_if {false} \
CONFIG.pcie_extended_tag {false} \
CONFIG.pf0_device_id {7022} \
CONFIG.pf0_link_status_slot_clock_config {false} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_cap_pba_bir {BAR_1} \
CONFIG.pf0_msix_cap_table_bir {BAR_1} \
CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \
CONFIG.pl_link_cap_max_link_width {X2} \
CONFIG.plltype {QPLL1} \
CONFIG.xdma_axi_intf_mm {AXI_Stream} \
] $xdma_0
# Create interface connections
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_ports M00_AXI_0] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net xdma_0_M_AXIS_H2C_0 [get_bd_intf_pins xdma_0/M_AXIS_H2C_0] [get_bd_intf_pins xdma_0/S_AXIS_C2H_0]
connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pcie_mgt_0] [get_bd_intf_pins xdma_0/pcie_mgt]
# Create port connections
connect_bd_net -net aclk1_0_1 [get_bd_ports aclk1_0] [get_bd_pins smartconnect_0/aclk1]
connect_bd_net -net sys_clk_0_1 [get_bd_ports pcie_clk] [get_bd_pins xdma_0/sys_clk]
connect_bd_net -net sys_rst_n_0_1 [get_bd_ports pcie_rst_n] [get_bd_pins xdma_0/sys_rst_n]
connect_bd_net -net usr_irq_req_0_1 [get_bd_ports usr_irq_req_0] [get_bd_pins xdma_0/usr_irq_req]
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins smartconnect_0/aclk] [get_bd_pins xdma_0/axi_aclk]
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins smartconnect_0/aresetn] [get_bd_pins xdma_0/axi_aresetn]
connect_bd_net -net xdma_0_user_lnk_up [get_bd_ports user_lnk_up_0] [get_bd_pins xdma_0/user_lnk_up]
connect_bd_net -net xdma_0_usr_irq_ack [get_bd_ports usr_irq_ack_0] [get_bd_pins xdma_0/usr_irq_ack]
# Create address segments
assign_bd_address -offset 0x44A00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_LITE] [get_bd_addr_segs M00_AXI_0/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
platform/xilinx/wr_pcie/wb_axi4lite_bridge.vhd 0 → 100644
View file @ 67892968
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.axi4_pkg.all;
entity xwb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
axi4_slave_i : in t_axi4_lite_slave_in_32;
axi4_slave_o : out t_axi4_lite_slave_out_32;
wb_master_o : buffer t_wishbone_master_out;
wb_master_i : in t_wishbone_master_in
);
end entity xwb_axi4lite_bridge;
architecture rtl of xwb_axi4lite_bridge is
type state_type is (IDLE, SR_SEND_ADDR, SR_GET_DATA, SR_SEND_DATA, SW_GET_DATA, SW_GET_ADDR, SW_SEND, SW_RESP);
signal prs, nxt : state_type;
begin
--state register for the Moore state machine, also has a timeout counter.
state_register : process(clk_sys_i,rst_n_i) is
variable count : unsigned(10 downto 0);
begin
if rst_n_i = '0' then
prs <= IDLE;
count := (others => '0');
elsif rising_edge(clk_sys_i) then
if prs /= IDLE then
count := count + 1;
else
count := (others => '0');
end if;
if count > 100 then
prs <= IDLE;
else
prs <= nxt;
end if;
end if;
end process state_register;
--next state decoder for the Moore state machine.
next_state_decoder : process(prs, wb_master_i, axi4_slave_i) is
begin
case prs is
when IDLE =>
if axi4_slave_i.awvalid = '1' and axi4_slave_i.wvalid = '1'then
nxt <= SW_SEND;
elsif axi4_slave_i.awvalid = '0' and axi4_slave_i.wvalid = '1' then
nxt <= SW_GET_ADDR;
elsif axi4_slave_i.awvalid = '1' and axi4_slave_i.wvalid = '0' then
nxt <= SW_GET_DATA;
elsif axi4_slave_i.arvalid = '1' then
nxt <= SR_SEND_ADDR;
else
nxt <= IDLE;
end if;
when SW_GET_ADDR =>
if axi4_slave_i.awvalid = '1' then
nxt <= SW_SEND;
else
nxt <= SW_GET_ADDR;
end if;
when SW_GET_DATA =>
if axi4_slave_i.wvalid = '1' then
nxt <= SW_SEND;
else
nxt <= SW_GET_DATA;
end if;
when SW_SEND =>
if wb_master_i.ack = '1' or wb_master_i.stall = '0' then
nxt <= SW_RESP;
else
nxt <= SW_SEND;
end if;
when SR_SEND_ADDR =>
if wb_master_i.stall = '0' then
nxt <= SR_GET_DATA;
else
nxt <= SR_SEND_ADDR;
end if;
when SR_GET_DATA =>
if wb_master_i.ack = '1' then
nxt <= SR_SEND_DATA;
else
nxt <= SR_GET_DATA;
end if;
when SR_SEND_DATA =>
if axi4_slave_i.rready = '1' then
nxt <= IDLE;
else
nxt <= SR_SEND_DATA;
end if;
when SW_RESP =>
if axi4_slave_i.bready = '1' then
nxt <= IDLE;
else
nxt <= SW_RESP;
end if;
end case;
end process next_state_decoder;
--manages the Wishbone addres signal, sources it from the axi-read or write channel depending on the command.
addr_register : process(clk_sys_i, rst_n_i) is
begin
if rst_n_i = '0' then
wb_master_o.adr <= (others => '0');
elsif rising_edge(clk_sys_i) then
if axi4_slave_i.awvalid = '1' then
wb_master_o.adr <= axi4_slave_i.awaddr;
elsif prs = SW_RESP then
wb_master_o.adr <= (others => '0');
elsif axi4_slave_i.arvalid = '1' then
wb_master_o.adr <= axi4_slave_i.araddr;
elsif prs = SR_SEND_DATA then
wb_master_o.adr <= (others => '0');
end if;
end if;
end process addr_register;
--manages the two data registers, one for reading (and byte-validation) the other for writing.
data_register : process(clk_sys_i, rst_n_i) is
begin
if rst_n_i = '0' then
wb_master_o.dat <= (others => '0');
wb_master_o.sel <= (others => '0');
axi4_slave_o.rdata <= (others => '0');
elsif rising_edge(clk_sys_i) then
if axi4_slave_i.wvalid = '1' then
wb_master_o.dat <= axi4_slave_i.wdata;
wb_master_o.sel <= axi4_slave_i.wstrb;
elsif prs = SW_RESP then
wb_master_o.dat <= (others => '0');
wb_master_o.sel <= (others => '0');
end if;
if prs = SR_GET_DATA and wb_master_i.ack = '1' then
axi4_slave_o.rdata <= wb_master_i.dat;
elsif prs = IDLE then
axi4_slave_o.rdata <= (others => '0');
end if;
end if;
end process data_register;
--roughly convers wishbone error messages to axi-error mesages.
error_register : process(clk_sys_i, rst_n_i) is
begin
if rst_n_i = '0' then
axi4_slave_o.bresp <= "10";
axi4_slave_o.rresp <= "10";
elsif rising_edge(clk_sys_i) then
if prs = SW_SEND and wb_master_i.ack = '1' then
axi4_slave_o.bresp <= wb_master_i.err & '0';
axi4_slave_o.rresp <= "00";
elsif prs = SW_SEND and wb_master_i.ack = '1' then
axi4_slave_o.bresp <= "00";
axi4_slave_o.rresp <= wb_master_i.err & '0';
elsif prs = IDLE then
axi4_slave_o.bresp <= "00";
axi4_slave_o.rresp <= "00";
end if;
end if;
end process error_register;
--AXI READ RELATED SIGNALS
axi4_slave_o.arready <= '1' when rst_n_i = '1' and prs = IDLE else '0';
axi4_slave_o.rvalid <= '1' when prs = SR_SEND_DATA else '0';
axi4_slave_o.rlast <= '1' when prs = SR_SEND_DATA else '0';
--AXI WRITE RELATED SIGNALS
axi4_slave_o.awready <= '1' when rst_n_i = '1' and (prs = IDLE or prs = SW_GET_ADDR) else '0';
axi4_slave_o.wready <= '1' when rst_n_i = '1' and (prs = IDLE or prs = SW_GET_DATA) else '0';
axi4_slave_o.bvalid <= '1' when prs = SW_RESP else '0';
--WISHBONE RELATED SIGNALS
wb_master_o.we <= '1' when prs = SW_SEND else '0';
wb_master_o.cyc <= '1' when prs = SR_SEND_ADDR or prs = SR_GET_DATA or prs = SW_SEND else '0';
wb_master_o.stb <= '1' when prs = SR_SEND_ADDR or prs = SW_SEND else '0';
end architecture rtl;
\ No newline at end of file
top/spec7_write_design/spec7_write_top.vhd
View file @ 67892968
......@@ -180,7 +180,19 @@ entity spec7_write_top is
-- EEPROM (24AA64 Addr 1010.000x) and
-- Unique ID (24AA025EU48, Addr 1010.001x).
scl_b : inout std_logic;
sda_b : inout std_logic
sda_b : inout std_logic;
---------------------------------------------------------------------------
-- PCIe interface
---------------------------------------------------------------------------
pci_clk_n : in std_logic;
pci_clk_p : in std_logic;
perst_n : in std_logic;
rxn : in std_logic_vector(1 downto 0);
rxp : in std_logic_vector(1 downto 0);
txn : out std_logic_vector(1 downto 0);
txp : out std_logic_vector(1 downto 0)
);
end entity spec7_write_top;
......@@ -254,6 +266,19 @@ architecture top of spec7_write_top is
-- DIO Mezzanine
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
--Axi4
signal m_axil_i : t_axi4_lite_master_in_32;
signal m_axil_o : t_axi4_lite_master_out_32;
signal axi_h2c_fifo_64, axi_c2h_fifo_64 : t_axis_64;
--Wishbone
signal wb_master_i : t_wishbone_master_in;
signal wb_master_o : t_wishbone_master_out;
--PCIe
signal pci_clk : std_logic;
component pll_62m5_500m is
port (
......@@ -281,6 +306,71 @@ begin -- architecture top
wdog_n_o <= '1';
-- prsnt_m2c_l_i isn't used but must be defined as input.
pci_clk_buf : IBUFDS_GTE2
port map(
I => pci_clk_p,
IB => pci_clk_n,
O => pci_clk,
ODIV2 => open,
CEB => '0'
);
Pcie: Pcie_wrapper
port map (
M00_AXI_0_araddr => m_axil_o.araddr,
M00_AXI_0_arburst => open,
M00_AXI_0_arcache => open,
M00_AXI_0_arlen => open,
M00_AXI_0_arlock => open,
M00_AXI_0_arprot => open,
M00_AXI_0_arqos => open,
M00_AXI_0_arready => m_axil_i.arready,
M00_AXI_0_arsize => open,
M00_AXI_0_arvalid => m_axil_o.arvalid,
M00_AXI_0_awaddr => m_axil_o.awaddr,
M00_AXI_0_awburst => open,
M00_AXI_0_awcache => open,
M00_AXI_0_awlen => open,
M00_AXI_0_awlock => open,
M00_AXI_0_awprot => open,
M00_AXI_0_awqos => open,
M00_AXI_0_awready => m_axil_i.awready,
M00_AXI_0_awsize => open,
M00_AXI_0_awvalid => m_axil_o.awvalid,
M00_AXI_0_bready => m_axil_o.bready,
M00_AXI_0_bresp => m_axil_i.bresp,
M00_AXI_0_bvalid => m_axil_i.bvalid,
M00_AXI_0_rdata => m_axil_i.rdata,
M00_AXI_0_rlast => m_axil_i.rlast,
M00_AXI_0_rready => m_axil_o.rready,
M00_AXI_0_rresp => m_axil_i.rresp,
M00_AXI_0_rvalid => m_axil_i.rvalid,
M00_AXI_0_wdata => m_axil_o.wdata,
M00_AXI_0_wlast => m_axil_o.wlast,
M00_AXI_0_wready => m_axil_i.wready,
M00_AXI_0_wstrb => m_axil_o.wstrb,
M00_AXI_0_wvalid => m_axil_o.wvalid,
aclk1_0 => clk_sys_62m5,
pcie_mgt_0_rxn => rxn,
pcie_mgt_0_rxp => rxp,
pcie_mgt_0_txn => txn,
pcie_mgt_0_txp => txp,
pcie_clk => pci_clk,
pcie_rst_n => perst_n,
user_lnk_up_0 => open,
usr_irq_ack_0 => open,
usr_irq_req_0 => "0"
);
AXI2WB : xwb_axi4lite_bridge
port map(
clk_sys_i => clk_sys_62m5,
rst_n_i => reset_n_i,
axi4_slave_i => m_axil_o,
axi4_slave_o => m_axil_i,
wb_master_o => wb_master_o,
wb_master_i => wb_master_i
);
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
......@@ -303,7 +393,6 @@ begin -- architecture top
clk_ref_62m5_o => clk_ref_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_62m5_n_o => rst_ref_62m5_n,
dac_refclk_cs_n_o => dac_refclk_cs_n_o,
dac_refclk_sclk_o => dac_refclk_sclk_o,
dac_refclk_din_o => dac_refclk_din_o,
......@@ -345,6 +434,9 @@ begin -- architecture top
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- Wishbone
wb_slave_i => wb_master_o,
wb_slave_o => wb_master_i,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => open,
......
top/spec7_write_design/spec7_write_top.xdc
View file @ 67892968
......@@ -94,6 +94,27 @@ set_property IOSTANDARD LVCMOS18 [get_ports pll_refsel_o]
set_property PACKAGE_PIN A12 [get_ports pll_lock_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_lock_i]
# ---------------------------------------------------------------------------
# -- PCIe
# ---------------------------------------------------------------------------
# Bank 112 (GTX2)
set_property PACKAGE_PIN AB3 [get_ports {rxn[0]}]
set_property PACKAGE_PIN AB4 [get_ports {rxp[0]}]
set_property PACKAGE_PIN AA1 [get_ports {txn[0]}]
set_property PACKAGE_PIN AA2 [get_ports {txp[0]}]
set_property PACKAGE_PIN Y3 [get_ports {rxn[1]}]
set_property PACKAGE_PIN Y4 [get_ports {rxp[1]}]
set_property PACKAGE_PIN W1 [get_ports {txn[1]}]
set_property PACKAGE_PIN W2 [get_ports {txp[1]}]
set_property PACKAGE_PIN R6 [get_ports pci_clk_p]
set_property PACKAGE_PIN R5 [get_ports pci_clk_n]
create_clock -period 10.000 -name pci_clk_p [get_ports pci_clk_p]
set_property PACKAGE_PIN D13 [get_ports perst_n]
set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
......@@ -123,14 +144,6 @@ set_property IOSTANDARD LVCMOS18 [get_ports sfp_tx_disable_o]
set_property PACKAGE_PIN K13 [get_ports sfp_los_i]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_los_i]
# ---------------------------------------------------------------------------
# -- PCIe PERST#
# ---------------------------------------------------------------------------
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN D13 [get_ports perst_n]
#set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
# ---------------------------------------------------------------------------
# -- UART
# ---------------------------------------------------------------------------
......
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