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White Rabbit core collection
Commit 6c2c291b authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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arria2: backport changes from arria5

parent 739338ff
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Showing with 43 additions and 65 deletions
platform/altera/altera_pkg.vhd
View file @ 6c2c291b
......@@ -27,6 +27,7 @@ package wr_altera_pkg is
component dmtd_pll is -- arria2
port(
areset : in std_logic;
inclk0 : in std_logic := '0'; -- 20 MHz
c0 : out std_logic; -- 62.5 MHz
locked : out std_logic);
......@@ -42,6 +43,7 @@ package wr_altera_pkg is
component ref_pll is -- arria2
port(
areset : in std_logic;
inclk0 : in std_logic := '0'; -- 125 MHz
c0 : out std_logic; -- 125 MHz
c1 : out std_logic; -- 200 MHz
......@@ -71,6 +73,7 @@ package wr_altera_pkg is
component sys_pll is -- arria2
port(
areset : in std_logic;
inclk0 : in std_logic := '0'; -- 125 MHz
c0 : out std_logic; -- 62.5 MHz
c1 : out std_logic; -- 50 MHz
......@@ -129,6 +132,7 @@ package wr_altera_pkg is
locked_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
......
platform/altera/arria2_pll/dmtd_pll.txt
View file @ 6c2c291b
......@@ -57,7 +57,7 @@
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
......@@ -69,7 +69,7 @@
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "dmtd_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
......@@ -96,7 +96,7 @@
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
......@@ -137,14 +137,16 @@
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
-- Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
......
platform/altera/arria2_pll/ref_pll.txt
View file @ 6c2c291b
......@@ -77,7 +77,7 @@
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
......@@ -89,7 +89,7 @@
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "ref_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
......@@ -128,7 +128,7 @@
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
......@@ -169,11 +169,12 @@
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
-- Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
......@@ -184,6 +185,7 @@
-- Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
-- Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
......
platform/altera/arria2_pll/sys_pll.txt
View file @ 6c2c291b
......@@ -77,7 +77,7 @@
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
......@@ -89,7 +89,7 @@
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "sys_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
......@@ -128,7 +128,7 @@
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
......@@ -169,16 +169,18 @@
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
-- Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
......
platform/altera/wr_arria2_phy/arria2_rxclkout.txt deleted 100644 → 0
View file @ 739338ff
-- megafunction wizard: %ALTCLKCTRL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclkctrl
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Arria II GX" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 11.1SP1 cbx_altclkbuf 2011:11:23:21:11:17:SJ cbx_cycloneii 2011:11:23:21:11:17:SJ cbx_lpm_add_sub 2011:11:23:21:11:17:SJ cbx_lpm_compare 2011:11:23:21:11:17:SJ cbx_lpm_decode 2011:11:23:21:11:17:SJ cbx_lpm_mux 2011:11:23:21:11:17:SJ cbx_mgl 2011:11:23:21:12:03:SJ cbx_stratix 2011:11:23:21:11:17:SJ cbx_stratixii 2011:11:23:21:11:17:SJ cbx_stratixiii 2011:11:23:21:11:17:SJ cbx_stratixv 2011:11:23:21:11:17:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
-- Retrieval info: CONSTANT: clock_type STRING "Global Clock"
-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rxclkout.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rxclkout.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rxclkout.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rxclkout.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rxclkout_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriaii
platform/altera/wr_arria2_phy/wr_arria2_phy.qip
View file @ 6c2c291b
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_phy.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_phy_reconf.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_rxclkout.qip"]
platform/altera/wr_arria2_phy/wr_arria2_phy.tcl
View file @ 6c2c291b
set files { arria2_phy arria2_phy_reconf arria2_rxclkout }
set files { arria2_phy arria2_phy_reconf }
set dir [file dirname [info script]]
post_message "Testing for megawizard regeneration in $dir:$files"
......
platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
View file @ 6c2c291b
......@@ -56,6 +56,7 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
use work.altera_networks_pkg.all;
entity wr_arria2_phy is
generic (
......@@ -71,7 +72,8 @@ entity wr_arria2_phy is
loopen_i : in std_logic; -- local loopback enable (Tx->Rx), active hi
drop_link_i : in std_logic; -- Kill the link?
-- clocked by clk_pll_i
-- clocked by tx_clk_i
tx_clk_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0); -- data input (8 bits, not 8b10b-encoded)
tx_k_i : in std_logic; -- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_disparity_o : out std_logic; -- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
......@@ -90,12 +92,6 @@ end wr_arria2_phy;
architecture rtl of wr_arria2_phy is
component arria2_rxclkout
port(
inclk : in std_logic;
outclk : out std_logic);
end component;
component arria2_phy
port (
cal_blk_clk : in std_logic;
......@@ -157,6 +153,7 @@ architecture rtl of wr_arria2_phy is
signal clk_rx_gxb : std_logic; -- pre clkctrl
signal clk_rx : std_logic; -- global clock
signal clk_tx_gxb : std_logic; -- pre clkctrl
signal clk_tx : std_logic; -- local clock
signal pll_locked : std_logic;
signal rx_freqlocked : std_logic;
......@@ -164,7 +161,7 @@ architecture rtl of wr_arria2_phy is
type t_state is (WAIT_POWER, WAIT_CMU, WAIT_CONFIG, WAIT_LOCK, DONE);
signal rst_state : t_state := WAIT_POWER;
signal rst_delay : unsigned(8 downto 0); -- must span >= 4us
signal rst_delay : unsigned(8 downto 0) := (others => '1'); -- must span >= 4us
signal pll_powerdown : std_logic;
signal tx_digitalreset : std_logic; -- sys domain
signal rx_analogreset : std_logic; -- sys domain
......@@ -193,17 +190,22 @@ architecture rtl of wr_arria2_phy is
signal rx_gxb_syncstatus : std_logic;
signal rx_glbl_syncstatus : std_logic;
signal tx_enc_datain : std_logic_vector (9 downto 0); -- registered encoder output (clk_pll_i)
signal tx_enc_datain : std_logic_vector (9 downto 0); -- registered encoder output (tx_clk_i)
signal tx_gxb_datain : std_logic_vector (9 downto 0); -- clock transfer register (clk_tx)
begin
rx_rbclk_o <= clk_rx;
U_RxClkout : arria2_rxclkout
U_RxClkout : single_region
port map (
inclk => clk_rx_gxb,
outclk => clk_rx);
U_TxClkout : single_region
port map (
inclk => clk_tx_gxb,
outclk => clk_tx);
-- Altera PHY calibration block
U_Reconf : arria2_phy_reconf
port map (
......@@ -219,7 +221,7 @@ begin
pll_inclk => clk_pll_i,
rx_cruclk(0) => clk_cru_i,
-- Derived clocks used for tx/rx lines
tx_clkout(0) => clk_tx,
tx_clkout(0) => clk_tx_gxb,
pll_locked(0) => pll_locked,
rx_clkout(0) => clk_rx_gxb,
rx_freqlocked(0) => rx_freqlocked,
......@@ -250,7 +252,7 @@ begin
-- Encode the TX data
encoder : enc_8b10b
port map(
clk_i => clk_pll_i,
clk_i => tx_clk_i,
rst_n_i => tx_8b10b_rstn(0),
ctrl_i => tx_k_i,
in_8b_i => tx_data_i,
......@@ -374,9 +376,9 @@ begin
-- Generate reset for 8b10b encoder
p_pll_reset : process(clk_pll_i) is
p_pll_reset : process(tx_clk_i) is
begin
if rising_edge(clk_pll_i) then
if rising_edge(tx_clk_i) then
tx_8b10b_rstn <= (not tx_digitalreset) & tx_8b10b_rstn(tx_8b10b_rstn'left downto 1);
end if;
end process;
......@@ -404,20 +406,16 @@ begin
-- The disparity should be delayed for WR
tx_disparity_o <= tx_disp_pipe(2);
p_delay_disp : process(clk_pll_i)
p_delay_disp : process(tx_clk_i)
begin
if rising_edge(clk_pll_i) then
if rising_edge(tx_clk_i) then
tx_disp_pipe(1) <= tx_disp_pipe(0);
tx_disp_pipe(2) <= tx_disp_pipe(1);
end if;
end process;
-- Cross clock domain from pll_clk_i to tx_clk
-- These clocks are in phase copies of each other.
-- Ensure that clk_tx has GLOBAL_SIGNAL OFF
-- set_instance_assignment -name GLOBAL_SIGNAL OFF \
-- -from wr_gxb_phy_arriaii:wr_gxb_phy_arriaii_1|arria_phy:U_The_PHY|arria_phy_alt4gxb:arria_phy_alt4gxb_component|tx_clkout_int_wire[0] \
-- -to wr_gxb_phy_arriaii:wr_gxb_phy_arriaii_1|tx_gxb_datain[*]
-- Cross clock domain from tx_clk_i to tx_clk
-- These clocks have a fixed phase relationship.
p_tx_path : process(clk_tx) is
begin
if clk_tx'event and clk_tx = g_tx_latch_edge then
......
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