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White Rabbit core collection
Commit 715a8d4e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_endpoint: re-generated WB slave, replaced VLAN/PFilter registers by RW/RW… 

wr_endpoint: re-generated WB slave, replaced VLAN/PFilter registers by RW/RW types which get synthesized away when not used
parent e8dedd65
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modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 715a8d4e
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2012-03-16
-- Last update: 2012-06-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -251,15 +251,16 @@ package endpoint_private_pkg is
component ep_wishbone_controller
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
tx_clk_i : in std_logic;
ep_rmon_ram_addr_i : in std_logic_vector(4 downto 0);
ep_rmon_ram_data_o : out std_logic_vector(31 downto 0);
......
modules/wr_endpoint/ep_packet_filter.vhd
View file @ 715a8d4e
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2012-02-09
-- Last update: 2012-06-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -158,13 +158,23 @@ architecture behavioral of ep_packet_filter is
type t_state is (WAIT_FRAME, PROCESS_FRAME, GEN_OUTPUT);
signal stage1, stage2 : std_logic;
signal stage1, stage2 : std_logic;
signal r_pfcr1_mm_data_lsb : std_logic_vector(11 downto 0);
begin -- behavioral
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(regs_i.pfcr1_mm_data_lsb_wr_o = '1') then
r_pfcr1_mm_data_lsb <= regs_i.pfcr1_mm_data_lsb_o;
end if;
end if;
end process;
mm_write <= not regs_i.pfcr0_enable_o and regs_i.pfcr0_mm_write_o and regs_i.pfcr0_mm_write_wr_o;
mm_wdata <= regs_i.pfcr0_mm_data_msb_o & regs_i.pfcr1_mm_data_lsb_o;
mm_wdata <= regs_i.pfcr0_mm_data_msb_o & r_pfcr1_mm_data_lsb;
U_microcode_ram : generic_dpram
generic map (
......@@ -231,7 +241,7 @@ begin -- behavioral
if rising_edge(clk_rx_i) then
if rst_n_rx_i = '0' or done_int = '1' then
stage2 <= '0';
ir <= (others => '0');
ir <= (others => '0');
else
stage2 <= stage1;
ir <= mm_rdata;
......
modules/wr_endpoint/ep_registers_pkg.vhd
View file @ 715a8d4e
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Sun Oct 30 00:20:59 2011
-- Created : Wed Jun 27 11:19:13 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -26,10 +26,17 @@ package ep_wbgen2_pkg is
ecr_feat_ptp_i : std_logic;
ecr_feat_dpi_i : std_logic;
tscr_cs_done_i : std_logic;
tcar_pcp_map_i : std_logic_vector(23 downto 0);
fcr_rxpause_i : std_logic;
fcr_txpause_i : std_logic;
fcr_tx_thr_i : std_logic_vector(7 downto 0);
fcr_tx_quanta_i : std_logic_vector(15 downto 0);
mdio_asr_rdata_i : std_logic_vector(15 downto 0);
mdio_asr_ready_i : std_logic;
dsr_lstatus_i : std_logic;
dsr_lact_i : std_logic;
dmcr_en_i : std_logic;
dmcr_n_avg_i : std_logic_vector(11 downto 0);
dmsr_ps_val_i : std_logic_vector(23 downto 0);
dmsr_ps_rdy_i : std_logic;
end record;
......@@ -40,10 +47,17 @@ package ep_wbgen2_pkg is
ecr_feat_ptp_i => '0',
ecr_feat_dpi_i => '0',
tscr_cs_done_i => '0',
tcar_pcp_map_i => (others => '0'),
fcr_rxpause_i => '0',
fcr_txpause_i => '0',
fcr_tx_thr_i => (others => '0'),
fcr_tx_quanta_i => (others => '0'),
mdio_asr_rdata_i => (others => '0'),
mdio_asr_ready_i => '0',
dsr_lstatus_i => '0',
dsr_lact_i => '0',
dmcr_en_i => '0',
dmcr_n_avg_i => (others => '0'),
dmsr_ps_val_i => (others => '0'),
dmsr_ps_rdy_i => '0'
);
......@@ -80,11 +94,17 @@ package ep_wbgen2_pkg is
pfcr0_mm_data_msb_o : std_logic_vector(23 downto 0);
pfcr0_mm_data_msb_wr_o : std_logic;
pfcr1_mm_data_lsb_o : std_logic_vector(11 downto 0);
pfcr1_mm_data_lsb_wr_o : std_logic;
tcar_pcp_map_o : std_logic_vector(23 downto 0);
tcar_pcp_map_load_o : std_logic;
fcr_rxpause_o : std_logic;
fcr_rxpause_load_o : std_logic;
fcr_txpause_o : std_logic;
fcr_txpause_load_o : std_logic;
fcr_tx_thr_o : std_logic_vector(7 downto 0);
fcr_tx_thr_load_o : std_logic;
fcr_tx_quanta_o : std_logic_vector(15 downto 0);
fcr_tx_quanta_load_o : std_logic;
mach_o : std_logic_vector(15 downto 0);
macl_o : std_logic_vector(31 downto 0);
mdio_cr_data_o : std_logic_vector(15 downto 0);
......@@ -95,7 +115,9 @@ package ep_wbgen2_pkg is
dsr_lact_o : std_logic;
dsr_lact_load_o : std_logic;
dmcr_en_o : std_logic;
dmcr_en_load_o : std_logic;
dmcr_n_avg_o : std_logic_vector(11 downto 0);
dmcr_n_avg_load_o : std_logic;
dmsr_ps_rdy_o : std_logic;
dmsr_ps_rdy_load_o : std_logic;
end record;
......@@ -130,11 +152,17 @@ package ep_wbgen2_pkg is
pfcr0_mm_data_msb_o => (others => '0'),
pfcr0_mm_data_msb_wr_o => '0',
pfcr1_mm_data_lsb_o => (others => '0'),
pfcr1_mm_data_lsb_wr_o => '0',
tcar_pcp_map_o => (others => '0'),
tcar_pcp_map_load_o => '0',
fcr_rxpause_o => '0',
fcr_rxpause_load_o => '0',
fcr_txpause_o => '0',
fcr_txpause_load_o => '0',
fcr_tx_thr_o => (others => '0'),
fcr_tx_thr_load_o => '0',
fcr_tx_quanta_o => (others => '0'),
fcr_tx_quanta_load_o => '0',
mach_o => (others => '0'),
macl_o => (others => '0'),
mdio_cr_data_o => (others => '0'),
......@@ -145,12 +173,15 @@ package ep_wbgen2_pkg is
dsr_lact_o => '0',
dsr_lact_load_o => '0',
dmcr_en_o => '0',
dmcr_en_load_o => '0',
dmcr_n_avg_o => (others => '0'),
dmcr_n_avg_load_o => '0',
dmsr_ps_rdy_o => '0',
dmsr_ps_rdy_load_o => '0'
);
function "or" (left, right: t_ep_in_registers) return t_ep_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body ep_wbgen2_pkg is
......@@ -162,20 +193,39 @@ else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_ep_in_registers) return t_ep_in_registers is
variable tmp: t_ep_in_registers;
begin
tmp.ecr_feat_vlan_i := left.ecr_feat_vlan_i or right.ecr_feat_vlan_i;
tmp.ecr_feat_dmtd_i := left.ecr_feat_dmtd_i or right.ecr_feat_dmtd_i;
tmp.ecr_feat_ptp_i := left.ecr_feat_ptp_i or right.ecr_feat_ptp_i;
tmp.ecr_feat_dpi_i := left.ecr_feat_dpi_i or right.ecr_feat_dpi_i;
tmp.tscr_cs_done_i := left.tscr_cs_done_i or right.tscr_cs_done_i;
tmp.mdio_asr_rdata_i := left.mdio_asr_rdata_i or right.mdio_asr_rdata_i;
tmp.mdio_asr_ready_i := left.mdio_asr_ready_i or right.mdio_asr_ready_i;
tmp.dsr_lstatus_i := left.dsr_lstatus_i or right.dsr_lstatus_i;
tmp.dsr_lact_i := left.dsr_lact_i or right.dsr_lact_i;
tmp.dmsr_ps_val_i := left.dmsr_ps_val_i or right.dmsr_ps_val_i;
tmp.dmsr_ps_rdy_i := left.dmsr_ps_rdy_i or right.dmsr_ps_rdy_i;
tmp.ecr_feat_vlan_i := f_x_to_zero(left.ecr_feat_vlan_i) or f_x_to_zero(right.ecr_feat_vlan_i);
tmp.ecr_feat_dmtd_i := f_x_to_zero(left.ecr_feat_dmtd_i) or f_x_to_zero(right.ecr_feat_dmtd_i);
tmp.ecr_feat_ptp_i := f_x_to_zero(left.ecr_feat_ptp_i) or f_x_to_zero(right.ecr_feat_ptp_i);
tmp.ecr_feat_dpi_i := f_x_to_zero(left.ecr_feat_dpi_i) or f_x_to_zero(right.ecr_feat_dpi_i);
tmp.tscr_cs_done_i := f_x_to_zero(left.tscr_cs_done_i) or f_x_to_zero(right.tscr_cs_done_i);
tmp.tcar_pcp_map_i := f_x_to_zero(left.tcar_pcp_map_i) or f_x_to_zero(right.tcar_pcp_map_i);
tmp.fcr_rxpause_i := f_x_to_zero(left.fcr_rxpause_i) or f_x_to_zero(right.fcr_rxpause_i);
tmp.fcr_txpause_i := f_x_to_zero(left.fcr_txpause_i) or f_x_to_zero(right.fcr_txpause_i);
tmp.fcr_tx_thr_i := f_x_to_zero(left.fcr_tx_thr_i) or f_x_to_zero(right.fcr_tx_thr_i);
tmp.fcr_tx_quanta_i := f_x_to_zero(left.fcr_tx_quanta_i) or f_x_to_zero(right.fcr_tx_quanta_i);
tmp.mdio_asr_rdata_i := f_x_to_zero(left.mdio_asr_rdata_i) or f_x_to_zero(right.mdio_asr_rdata_i);
tmp.mdio_asr_ready_i := f_x_to_zero(left.mdio_asr_ready_i) or f_x_to_zero(right.mdio_asr_ready_i);
tmp.dsr_lstatus_i := f_x_to_zero(left.dsr_lstatus_i) or f_x_to_zero(right.dsr_lstatus_i);
tmp.dsr_lact_i := f_x_to_zero(left.dsr_lact_i) or f_x_to_zero(right.dsr_lact_i);
tmp.dmcr_en_i := f_x_to_zero(left.dmcr_en_i) or f_x_to_zero(right.dmcr_en_i);
tmp.dmcr_n_avg_i := f_x_to_zero(left.dmcr_n_avg_i) or f_x_to_zero(right.dmcr_n_avg_i);
tmp.dmsr_ps_val_i := f_x_to_zero(left.dmsr_ps_val_i) or f_x_to_zero(right.dmsr_ps_val_i);
tmp.dmsr_ps_rdy_i := f_x_to_zero(left.dmsr_ps_rdy_i) or f_x_to_zero(right.dmsr_ps_rdy_i);
return tmp;
end function;
end package body;
modules/wr_endpoint/ep_rx_path.vhd
View file @ 715a8d4e
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2012-01-23
-- Last update: 2012-06-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -87,7 +87,7 @@ entity ep_rx_path is
-- RMON/statistic counters signals
rmon_o : inout t_rmon_triggers;
regs_i : in t_ep_out_registers;
-- regs_o : out t_ep_in_registers;
regs_o : out t_ep_in_registers;
-------------------------------------------------------------------------------
-- RTU interface
......@@ -115,7 +115,7 @@ architecture behavioral of ep_rx_path is
rtu_full_i : in std_logic;
rtu_rq_valid_o : out std_logic);
end component;
component ep_rx_early_address_match
port (
clk_sys_i : in std_logic;
......@@ -174,7 +174,8 @@ architecture behavioral of ep_rx_path is
vid_o : out std_logic_vector(11 downto 0);
tag_done_o : out std_logic;
rmon_o : inout t_rmon_triggers;
regs_i : in t_ep_out_registers);
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers);
end component;
component ep_rx_oob_insert
......@@ -228,7 +229,7 @@ architecture behavioral of ep_rx_path is
ematch_is_pause_i : in std_logic;
rmon_o : out t_rmon_triggers);
end component;
component ep_rx_buffer
generic (
g_size : integer);
......@@ -241,7 +242,7 @@ architecture behavioral of ep_rx_path is
src_dreq_i : in std_logic;
level_o : out std_logic_vector(7 downto 0);
regs_i : in t_ep_out_registers;
rmon_o : out t_rmon_triggers);
rmon_o : out t_rmon_triggers);
end component;
type t_rx_deframer_state is (RXF_IDLE, RXF_DATA, RXF_FLUSH_STALL, RXF_FINISH_CYCLE, RXF_THROW_ERROR);
......@@ -331,10 +332,10 @@ begin -- behavioral
end generate gen_with_packet_filter;
gen_without_packet_filter : if(not g_with_dpi_classifier) generate
fab_pipe(2) <= fab_pipe(1);
pfilter_drop <= '0';
pfilter_done <= '1';
pfilter_pclass <=(others => '0');
fab_pipe(2) <= fab_pipe(1);
pfilter_drop <= '0';
pfilter_done <= '1';
pfilter_pclass <= (others => '0');
end generate gen_without_packet_filter;
......@@ -389,16 +390,17 @@ begin -- behavioral
vid_o => vlan_vid,
tag_done_o => vlan_tag_done,
rmon_o => rmon_o,
regs_i => regs_i);
regs_i => regs_i,
regs_o => regs_o);
end generate gen_with_vlan_unit;
gen_without_vlan_unit: if(not g_with_vlans) generate
fab_pipe(6) <= fab_pipe(5);
gen_without_vlan_unit : if(not g_with_vlans) generate
fab_pipe(6) <= fab_pipe(5);
dreq_pipe(5) <= dreq_pipe(6);
end generate gen_without_vlan_unit;
U_RTU_Header_Extract: ep_rtu_header_extract
U_RTU_Header_Extract : ep_rtu_header_extract
generic map (
g_with_rtu => g_with_rtu)
port map (
......@@ -411,7 +413,7 @@ begin -- behavioral
rtu_rq_o => rtu_rq_o,
rtu_full_i => rtu_full_i,
rtu_rq_valid_o => rtu_rq_valid_o);
U_Gen_Status : ep_rx_status_reg_insert
port map (
clk_sys_i => clk_sys_i,
......@@ -428,8 +430,8 @@ begin -- behavioral
ematch_is_pause_i => ematch_is_pause,
rmon_o => open);
gen_with_rx_buffer: if g_with_rx_buffer generate
U_Rx_Buffer: ep_rx_buffer
gen_with_rx_buffer : if g_with_rx_buffer generate
U_Rx_Buffer : ep_rx_buffer
generic map (
g_size => g_rx_buffer_size)
port map (
......@@ -444,11 +446,11 @@ begin -- behavioral
rmon_o => open);
end generate gen_with_rx_buffer;
gen_without_rx_buffer: if (not g_with_rx_buffer) generate
fab_pipe(9) <= fab_pipe(8);
gen_without_rx_buffer : if (not g_with_rx_buffer) generate
fab_pipe(9) <= fab_pipe(8);
dreq_pipe(8) <= dreq_pipe(9);
end generate gen_without_rx_buffer;
U_RX_Wishbone_Master : ep_rx_wb_master
generic map (
g_ignore_ack => true)
......
modules/wr_endpoint/ep_rx_vlan_unit.vhd
View file @ 715a8d4e
......@@ -25,7 +25,8 @@ entity ep_rx_vlan_unit is
tag_done_o : out std_logic;
rmon_o : inout t_rmon_triggers;
regs_i : in t_ep_out_registers
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers
);
end ep_rx_vlan_unit;
......@@ -54,6 +55,7 @@ architecture behavioral of ep_rx_vlan_unit is
signal prio_int : std_logic_vector(2 downto 0);
signal force_dvalid : std_logic;
signal r_tcar_pcp_map : std_logic_vector(23 downto 0);
procedure f_vlan_decision
(tag_type : t_tag_type;
......@@ -85,9 +87,9 @@ architecture behavioral of ep_rx_vlan_unit is
case tag_type is
when NONE =>
admit := '0';
when PRIO=>
when PRIO =>
admit := '0';
when VLAN=>
when VLAN =>
admit := '1';
use_pvid := '0';
use_fixed_prio := '0';
......@@ -101,10 +103,10 @@ architecture behavioral of ep_rx_vlan_unit is
when NONE =>
admit := '1';
use_pvid := '1'; use_fixed_prio := '1';
when PRIO=>
when PRIO =>
admit := '1';
use_pvid := '1'; use_fixed_prio := '0';
when VLAN=>
when VLAN =>
admit := '1';
use_pvid := '0'; use_fixed_prio := '0';
when NULL_VLAN =>
......@@ -117,11 +119,11 @@ architecture behavioral of ep_rx_vlan_unit is
admit := '1';
use_pvid := '0';
use_fixed_prio := '1';
when PRIO=>
when PRIO =>
admit := '1';
use_pvid := '0';
use_fixed_prio := '0';
when VLAN=>
when VLAN =>
admit := '1';
use_pvid := '0';
use_fixed_prio := '0';
......@@ -354,9 +356,17 @@ begin -- behavioral
-- Process: p_map_prio_to_tc
-- Maps the PCP value from the 802.1q header into a traffic class for further
-- processing. The mapping table is stored in TCAR register.
regs_o.tcar_pcp_map_i <= r_tcar_pcp_map;
p_map_prio_to_tc : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(regs_i.tcar_pcp_map_load_o = '1') then
r_tcar_pcp_map <= regs_i.tcar_pcp_map_o;
end if;
if(rst_n_i = '0' or regs_i.ecr_rx_en_o = '0' or snk_fab_i.sof = '1')then
tag_done_o <= '0';
elsif(hdr_offset(9) = '1') then
......@@ -364,14 +374,14 @@ begin -- behavioral
-- certainly valid
tag_done_o <= '1';
case prio_int is
when "000" => tclass_o <= regs_i.tcar_pcp_map_o(2 downto 0);
when "001" => tclass_o <= regs_i.tcar_pcp_map_o(5 downto 3);
when "010" => tclass_o <= regs_i.tcar_pcp_map_o(8 downto 6);
when "011" => tclass_o <= regs_i.tcar_pcp_map_o(11 downto 9);
when "100" => tclass_o <= regs_i.tcar_pcp_map_o(14 downto 12);
when "101" => tclass_o <= regs_i.tcar_pcp_map_o(17 downto 15);
when "110" => tclass_o <= regs_i.tcar_pcp_map_o(20 downto 18);
when "111" => tclass_o <= regs_i.tcar_pcp_map_o(23 downto 21);
when "000" => tclass_o <= r_tcar_pcp_map(2 downto 0);
when "001" => tclass_o <= r_tcar_pcp_map(5 downto 3);
when "010" => tclass_o <= r_tcar_pcp_map(8 downto 6);
when "011" => tclass_o <= r_tcar_pcp_map(11 downto 9);
when "100" => tclass_o <= r_tcar_pcp_map(14 downto 12);
when "101" => tclass_o <= r_tcar_pcp_map(17 downto 15);
when "110" => tclass_o <= r_tcar_pcp_map(20 downto 18);
when "111" => tclass_o <= r_tcar_pcp_map(23 downto 21);
when others => tclass_o <= "XXX"; -- packet probably contains porn
end case;
end if;
......
modules/wr_endpoint/ep_wishbone_controller.wb
View file @ 715a8d4e
......@@ -377,9 +377,7 @@ peripheral {
size = 12;
name = "Microcode Memory Data (12 LSBs)";
prefix = "MM_DATA_LSB";
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = PASS_THROUGH;
};
};
......@@ -395,7 +393,8 @@ peripheral {
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
......@@ -411,8 +410,9 @@ peripheral {
0: disable reception of pause frames";
prefix = "RXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
type = BIT;
load = LOAD_EXT;
};
field {
......@@ -421,8 +421,9 @@ peripheral {
0: disable transmission of pause frames";
prefix = "TXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
type = BIT;
load = LOAD_EXT;
};
......@@ -431,10 +432,11 @@ peripheral {
description = "Defines the percentage of space occupied in the RX buffer which triggers the transmission of a PAUSE frame. 0 = empty buffer, 255 = full buffer";
prefix = "TX_THR";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
type = SLV;
size = 8;
align = 8;
load = LOAD_EXT;
};
field {
......@@ -442,10 +444,11 @@ peripheral {
description = "Defines the quanta value carried bypause frames sent by the Endpoint";
prefix = "TX_QUANTA";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
type = SLV;
size = 16;
align = 16;
load = LOAD_EXT;
};
};
......@@ -594,8 +597,9 @@ peripheral {
description = "1: enables DMTD phase measurement";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
......@@ -605,8 +609,9 @@ peripheral {
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 715a8d4e
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-03-21
-- Last update: 2012-06-27
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -68,10 +68,10 @@ entity wr_endpoint is
clk_ref_i : in std_logic;
-- reference clock / 2 (62.5 MHz, in-phase with refclk)
clk_sys_i : in std_logic;
clk_sys_i : in std_logic;
-- DMTD offset clock for phase tracking - used only if g_with_dmtd == true
clk_dmtd_i : in std_logic;
clk_dmtd_i : in std_logic;
-- sync reset (clk_sys_i domain), active LO
rst_n_i : in std_logic;
......@@ -148,9 +148,9 @@ entity wr_endpoint is
-------------------------------------------------------------------------------
-- Port ID value
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_port_id_o : out std_logic_vector(4 downto 0);
-- Frame ID value
txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
-- TX Timestamp and correctness info
txtsu_ts_value_o : out std_logic_vector(28 + 4 - 1 downto 0);
......@@ -306,6 +306,7 @@ architecture syn of wr_endpoint is
fc_buffer_occupation_o : out std_logic_vector(7 downto 0);
rmon_o : inout t_rmon_triggers;
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers;
rtu_rq_o : out t_ep_internal_rtu_request;
rtu_full_i : in std_logic;
rtu_rq_valid_o : out std_logic);
......@@ -442,6 +443,7 @@ architecture syn of wr_endpoint is
signal regs_towb : t_ep_in_registers;
signal regs_towb_ep : t_ep_in_registers;
signal regs_towb_tsu : t_ep_in_registers;
signal regs_towb_rpath: t_ep_in_registers;
-------------------------------------------------------------------------------
......@@ -497,6 +499,9 @@ architecture syn of wr_endpoint is
signal phase_meas : std_logic_vector(31 downto 0);
signal phase_meas_p : std_logic;
signal validity_cntr : unsigned(1 downto 0);
signal r_dmcr_en : std_logic;
signal r_dmcr_n_avg : std_logic_vector(11 downto 0);
signal rtu_rq : t_ep_internal_rtu_request;
signal dvalid_tx, dvalid_rx : std_logic;
......@@ -663,6 +668,7 @@ begin
rmon_o => rmon,
regs_i => regs_fromwb,
regs_o =>regs_towb_rpath,
rtu_full_i => rtu_full_i,
rtu_rq_o => rtu_rq,
......@@ -755,14 +761,14 @@ begin
rst_n_sys_i => rst_n_sys,
rst_n_ref_i => rst_n_ref,
pps_csync_p1_i => pps_csync_p1_i,
pps_valid_i => pps_valid_i,
pps_valid_i => pps_valid_i,
tx_timestamp_trigger_p_a_i => txpcs_timestamp_trigger_p_a,
rx_timestamp_trigger_p_a_i => rxpcs_timestamp_trigger_p_a,
rxts_timestamp_o => rxpcs_timestamp_value,
rxts_timestamp_valid_o => rxpcs_timestamp_valid,
rxts_timestamp_stb_o => rxpcs_timestamp_stb,
rxts_timestamp_stb_o => rxpcs_timestamp_stb,
txts_timestamp_o => txts_timestamp_value,
txts_timestamp_valid_o => txts_timestamp_valid,
......@@ -802,16 +808,17 @@ begin
U_WB_SLAVE : ep_wishbone_controller
port map (
rst_n_i => rst_n_sys,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_in.adr(5 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
rst_n_i => rst_n_sys,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(5 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => open,
tx_clk_i => clk_ref_i,
......@@ -830,7 +837,7 @@ begin
wb_out.err <= '0';
wb_out.int <= '0';
regs_towb <= regs_towb_ep or regs_towb_tsu;
regs_towb <= regs_towb_ep or regs_towb_tsu or regs_towb_rpath;
p_link_activity : process(clk_sys_i)
......@@ -867,11 +874,16 @@ begin
clk_dmtd_i => clk_dmtd_i,
rst_n_i => rst_n_i,
en_i => regs_fromwb.dmcr_en_o,
navg_i => regs_fromwb.dmcr_n_avg_o,
en_i => r_dmcr_en,
navg_i => r_dmcr_n_avg,
phase_meas_o => phase_meas,
phase_meas_p_o => phase_meas_p);
regs_towb.dmcr_en_i <= r_dmcr_en;
regs_towb.dmcr_n_avg_i <= r_dmcr_n_avg;
p_dmtd_update : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -880,7 +892,12 @@ begin
regs_towb_ep.dmsr_ps_rdy_i <= '0';
else
if(regs_fromwb.dmcr_en_o = '0') then
if(regs_fromwb.dmcr_en_load_o = '1') then
r_dmcr_en <= regs_fromwb.dmcr_en_o;
r_dmcr_n_avg <= regs_fromwb.dmcr_n_avg_o;
end if;
if(r_dmcr_en = '0') then
validity_cntr <= (others => '0');
regs_towb_ep.dmsr_ps_rdy_i <= '0';
elsif(regs_fromwb.dmsr_ps_rdy_o = '1' and regs_fromwb.dmsr_ps_rdy_load_o = '1') then
......
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