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White Rabbit core collection
Commit 71f2a5e3 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrcore_v2: deadbee generates resetting signal, adding xwr wrapper for syscon

parent f0600e56
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Showing with 144 additions and 16 deletions
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ 71f2a5e3
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Tue Oct 25 21:17:25 2011
-- Created : Mon Nov 7 14:48:09 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -40,8 +40,9 @@ package sysc_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_sysc_out_registers is record
rstr_hrst_o : std_logic_vector(31 downto 0);
rstr_hrst_wr_o : std_logic;
rstr_trig_o : std_logic_vector(27 downto 0);
rstr_trig_wr_o : std_logic;
rstr_rst_o : std_logic;
gpsr_led_stat_o : std_logic;
gpsr_led_link_o : std_logic;
gpsr_fmc_scl_o : std_logic;
......@@ -57,8 +58,9 @@ package sysc_wbgen2_pkg is
end record;
constant c_sysc_out_registers_init_value: t_sysc_out_registers := (
rstr_hrst_o => (others => '0'),
rstr_hrst_wr_o => '0',
rstr_trig_o => (others => '0'),
rstr_trig_wr_o => '0',
rstr_rst_o => '0',
gpsr_led_stat_o => '0',
gpsr_led_link_o => '0',
gpsr_fmc_scl_o => '0',
......
modules/wrc_core/wrc_syscon_wb.vhd
View file @ 71f2a5e3
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Tue Oct 25 21:17:25 2011
-- Created : Mon Nov 7 14:48:09 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -36,6 +36,7 @@ end wrc_syscon_wb;
architecture syn of wrc_syscon_wb is
signal sysc_rstr_rst_int : std_logic ;
signal sysc_gpsr_led_stat_dly0 : std_logic ;
signal sysc_gpsr_led_stat_int : std_logic ;
signal sysc_gpsr_led_link_dly0 : std_logic ;
......@@ -80,7 +81,8 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
regs_o.rstr_hrst_wr_o <= '0';
regs_o.rstr_trig_wr_o <= '0';
sysc_rstr_rst_int <= '0';
sysc_gpsr_led_stat_int <= '0';
sysc_gpsr_led_link_int <= '0';
regs_o.gpsr_fmc_scl_load_o <= '0';
......@@ -97,7 +99,7 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.rstr_hrst_wr_o <= '0';
regs_o.rstr_trig_wr_o <= '0';
sysc_gpsr_led_stat_int <= '0';
sysc_gpsr_led_link_int <= '0';
regs_o.gpsr_fmc_scl_load_o <= '0';
......@@ -109,7 +111,7 @@ begin
sysc_gpcr_fmc_sda_int <= '0';
ack_in_progress <= '0';
else
regs_o.rstr_hrst_wr_o <= '0';
regs_o.rstr_trig_wr_o <= '0';
regs_o.gpsr_fmc_scl_load_o <= '0';
regs_o.gpsr_fmc_sda_load_o <= '0';
end if;
......@@ -118,8 +120,11 @@ begin
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
regs_o.rstr_hrst_wr_o <= '1';
regs_o.rstr_trig_wr_o <= '1';
rddata_reg(28) <= 'X';
sysc_rstr_rst_int <= wrdata_reg(28);
else
rddata_reg(28) <= sysc_rstr_rst_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -148,7 +153,6 @@ begin
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
......@@ -352,7 +356,9 @@ begin
wb_data_o <= rddata_reg;
-- Reset trigger
-- pass-through field: Reset trigger in register: Syscon reset register
regs_o.rstr_hrst_o <= wrdata_reg(31 downto 0);
regs_o.rstr_trig_o <= wrdata_reg(27 downto 0);
-- Reset line state value
regs_o.rstr_rst_o <= sysc_rstr_rst_int;
-- Status LED
process (bus_clock_int, rst_n_i)
begin
......
modules/wrc_core/wrc_syscon_wb.wb
View file @ 71f2a5e3
......@@ -12,10 +12,19 @@ peripheral {
field {
name = "Reset trigger";
prefix = "HRST";
description = "Write 0xdeadbeef to reset the WR Core";
prefix = "TRIG";
description = "Write 0xdeadbee latch the state of RSTR.RST to the reset line of the LM32 CPU.";
type = PASS_THROUGH;
size = 32;
size = 28;
};
field {
name = "Reset line state value";
prefix = "RST";
description = "State of the reset line";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......@@ -179,4 +188,4 @@ peripheral {
};
};
\ No newline at end of file
};
modules/wrc_core/xwr_syscon_wb.vhd 0 → 100644
View file @ 71f2a5e3
-------------------------------------------------------------------------------
-- Title : WhiteRabbit Syscon
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : xwr_syscon_wb.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-11-07
-- Last update: 2011-11-07
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Wrapper for wrc_syscon_wb. Uses types instead of std_logic signals and
-- can use pipelined or classic wishbone.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-11-07 1.0 greg.d Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
entity xwr_syscon_wb is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
regs_i : in t_sysc_in_registers;
regs_o : out t_sysc_out_registers
);
end xwr_syscon_wb;
architecture syn of xwr_syscon_wb is
component wrc_syscon_wb
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
regs_i : in t_sysc_in_registers;
regs_o : out t_sysc_out_registers
);
end component;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin
U_Adapter : wb_slave_adapter
generic map(
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => slave_i.adr,
sl_dat_i => slave_i.dat,
sl_sel_i => slave_i.sel,
sl_cyc_i => slave_i.cyc,
sl_stb_i => slave_i.stb,
sl_we_i => slave_i.we,
sl_dat_o => slave_o.dat,
sl_ack_o => slave_o.ack,
sl_stall_o => slave_o.stall);
WRAPPED_SYSCON: wrc_syscon_wb
port map(
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_in.adr(2 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
regs_i => regs_i,
regs_o => regs_o);
wb_in.adr(c_wishbone_address_width-1 downto 3) <= (others=>'0');
end syn;
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