Skip to content

W
White Rabbit core collection
Commit 73d02fe3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

wr_endpoint: ep_rx_path: increased RX fifo threshold

parent 2f490c06
Hide whitespace changes
Inline Side-by-side
Showing with 2 additions and 2 deletions
modules/wr_endpoint/ep_rx_path.vhd
View file @ 73d02fe3
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2009-06-22 -- Created : 2009-06-22
-- Last update: 2011-10-18 -- Last update: 2011-10-27
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -337,7 +337,7 @@ begin -- behavioral ...@@ -337,7 +337,7 @@ begin -- behavioral
full_o => open, full_o => open,
empty_o => open, empty_o => open,
almostfull_o => pcs_fifo_almostfull_o, almostfull_o => pcs_fifo_almostfull_o,
pass_threshold_i => std_logic_vector(to_unsigned(12, 6))); -- fixme: add pass_threshold_i => std_logic_vector(to_unsigned(24, 6))); -- fixme: add
-- register -- register
U_Insert_OOB : ep_rx_oob_insert U_Insert_OOB : ep_rx_oob_insert
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment