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White Rabbit core collection
Commit 7621f92c authored by Peter Jansweijer's avatar Peter Jansweijer
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gthe4 reference frequency 100 MHz (was 125 MHz)

parent f319ee50
Pipeline #4776 failed with stage
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    Showing with 8 additions and 8 deletions
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.v
    View file @ 7621f92c
    ......@@ -55,9 +55,9 @@
    (* CORE_GENERATION_INFO = "gtwizard_ultrascale_2,gtwizard_ultrascale_2_gtwizard_top,{x_ipProduct=Vivado 2022.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=gtwizard_ultrascale,x_ipVersion=1.7,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_CHANNEL_ENABLE=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,C_PCIE_ENABLE=0,C_PCIE_CORECLK_FREQ=250,C_COMMON_SCALING_FACTOR=\
    1,C_CPLL_VCO_FREQUENCY=2500.0,C_FORCE_COMMONS=0,C_FREERUN_FREQUENCY=62.5,C_GT_TYPE=2,C_GT_REV=57,C_INCLUDE_CPLL_CAL=2,C_ENABLE_COMMON_USRCLK=0,C_USER_GTPOWERGOOD_DELAY_EN=1,C_SIM_CPLL_CAL_BYPASS=1,C_LOCATE_COMMON=0,C_LOCATE_RESET_CONTROLLER=0,C_LOCATE_USER_DATA_WIDTH_SIZING=0,C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_IN_SYSTEM_IBERT_CORE=1,C_LOCATE_RX_USER_CLOCKING=0,C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_TX_USER_CLOCKING=0,C_RESET_CONTROLLER_INSTANCE_CTRL=0,C_RX_BUFFBYPASS_MODE=0\
    ,C_RX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_RX_BUFFER_MODE=0,C_RX_CB_DISP=00000000,C_RX_CB_K=00000000,C_RX_CB_MAX_LEVEL=1,C_RX_CB_LEN_SEQ=1,C_RX_CB_NUM_SEQ=0,C_RX_CB_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_CC_DISP=00000000,C_RX_CC_ENABLE=0,C_RESET_SEQUENCE_INTERVAL=0,C_RX_CC_K=00000000,C_RX_CC_LEN_SEQ=1,C_RX_CC_NUM_SEQ=0,C_RX_CC_PERIODICITY=5000,C_RX_CC_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_COMMA_M_EN\
    ABLE=0,C_RX_COMMA_M_VAL=1010000011,C_RX_COMMA_P_ENABLE=0,C_RX_COMMA_P_VAL=0101111100,C_RX_DATA_DECODING=0,C_RX_ENABLE=1,C_RX_INT_DATA_WIDTH=20,C_RX_LINE_RATE=1.25,C_RX_MASTER_CHANNEL_IDX=0,C_RX_OUTCLK_BUFG_GT_DIV=1,C_RX_OUTCLK_FREQUENCY=62.5000000,C_RX_OUTCLK_SOURCE=1,C_RX_PLL_TYPE=2,C_RX_RECCLK_OUTPUT=0x000000000000000000000000000000000000000000000000,C_RX_REFCLK_FREQUENCY=125,C_RX_SLIDE_MODE=1,C_RX_USER_CLOCKING_CONTENTS=0,C_RX_USER_CLOCKING_INSTANCE_CTRL=0,C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCL\
    ABLE=0,C_RX_COMMA_M_VAL=1010000011,C_RX_COMMA_P_ENABLE=0,C_RX_COMMA_P_VAL=0101111100,C_RX_DATA_DECODING=0,C_RX_ENABLE=1,C_RX_INT_DATA_WIDTH=20,C_RX_LINE_RATE=1.25,C_RX_MASTER_CHANNEL_IDX=0,C_RX_OUTCLK_BUFG_GT_DIV=1,C_RX_OUTCLK_FREQUENCY=62.5000000,C_RX_OUTCLK_SOURCE=1,C_RX_PLL_TYPE=2,C_RX_RECCLK_OUTPUT=0x000000000000000000000000000000000000000000000000,C_RX_REFCLK_FREQUENCY=100,C_RX_SLIDE_MODE=1,C_RX_USER_CLOCKING_CONTENTS=0,C_RX_USER_CLOCKING_INSTANCE_CTRL=0,C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCL\
    K=1,C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_RX_USER_CLOCKING_SOURCE=0,C_RX_USER_DATA_WIDTH=20,C_RX_USRCLK_FREQUENCY=62.5000000,C_RX_USRCLK2_FREQUENCY=62.5000000,C_SECONDARY_QPLL_ENABLE=0,C_SECONDARY_QPLL_REFCLK_FREQUENCY=257.8125,C_TOTAL_NUM_CHANNELS=1,C_TOTAL_NUM_COMMONS=0,C_TOTAL_NUM_COMMONS_EXAMPLE=0,C_TXPROGDIV_FREQ_ENABLE=0,C_TXPROGDIV_FREQ_SOURCE=2,C_TXPROGDIV_FREQ_VAL=62.5,C_TX_BUFFBYPASS_MODE=0,C_TX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_TX_BUFFER_MODE=0,C_TX_DATA_ENCODING=0,C_TX_ENABLE=1\
    ,C_TX_INT_DATA_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX=0,C_TX_OUTCLK_BUFG_GT_DIV=1,C_TX_OUTCLK_FREQUENCY=62.5000000,C_TX_OUTCLK_SOURCE=4,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=125,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=1,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=20,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
    ,C_TX_INT_DATA_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX=0,C_TX_OUTCLK_BUFG_GT_DIV=1,C_TX_OUTCLK_FREQUENCY=62.5000000,C_TX_OUTCLK_SOURCE=4,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=100,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=1,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=20,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
    (* DowngradeIPIdentifiedWarnings = "yes" *)
    module gtwizard_ultrascale_2 (
    gtwiz_userclk_tx_reset_in,
    ......@@ -229,7 +229,7 @@ output wire [0 : 0] txresetdone_out;
    .C_RX_OUTCLK_SOURCE(1),
    .C_RX_PLL_TYPE(2),
    .C_RX_RECCLK_OUTPUT(192'H000000000000000000000000000000000000000000000000),
    .C_RX_REFCLK_FREQUENCY(125),
    .C_RX_REFCLK_FREQUENCY(100),
    .C_RX_SLIDE_MODE(1),
    .C_RX_USER_CLOCKING_CONTENTS(0),
    .C_RX_USER_CLOCKING_INSTANCE_CTRL(0),
    ......@@ -259,7 +259,7 @@ output wire [0 : 0] txresetdone_out;
    .C_TX_OUTCLK_FREQUENCY(62.5000000),
    .C_TX_OUTCLK_SOURCE(4),
    .C_TX_PLL_TYPE(2),
    .C_TX_REFCLK_FREQUENCY(125),
    .C_TX_REFCLK_FREQUENCY(100),
    .C_TX_USER_CLOCKING_CONTENTS(0),
    .C_TX_USER_CLOCKING_INSTANCE_CTRL(0),
    .C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK(1),
    ......
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
    View file @ 7621f92c
    ......@@ -499,7 +499,7 @@ gtwizard_ultrascale_v1_7_13_gthe4_channel #(
    .GTHE4_CHANNEL_CPLL_CFG2 (16'b0000000000000010),
    .GTHE4_CHANNEL_CPLL_CFG3 (16'b0000000000000000),
    .GTHE4_CHANNEL_CPLL_FBDIV (5),
    .GTHE4_CHANNEL_CPLL_FBDIV_45 (4),
    .GTHE4_CHANNEL_CPLL_FBDIV_45 (5),
    .GTHE4_CHANNEL_CPLL_INIT_CFG0 (16'b0000001010110010),
    .GTHE4_CHANNEL_CPLL_LOCK_CFG (16'b0000000111101000),
    .GTHE4_CHANNEL_CPLL_REFCLK_DIV (1),
    ......@@ -1044,7 +1044,7 @@ gtwizard_ultrascale_v1_7_13_gthe4_channel #(
    .GTHE4_CHANNEL_RX_BIAS_CFG0 (16'b0001010101010100),
    .GTHE4_CHANNEL_RX_BUFFER_CFG (6'b000000),
    .GTHE4_CHANNEL_RX_CAPFF_SARC_ENB (1'b0),
    .GTHE4_CHANNEL_RX_CLK25_DIV (5),
    .GTHE4_CHANNEL_RX_CLK25_DIV (4),
    .GTHE4_CHANNEL_RX_CLKMUX_EN (1'b1),
    .GTHE4_CHANNEL_RX_CLK_SLIP_OVRD (5'b00000),
    .GTHE4_CHANNEL_RX_CM_BUF_CFG (4'b1010),
    ......@@ -1301,7 +1301,7 @@ gtwizard_ultrascale_v1_7_13_gthe4_channel #(
    .GTHE4_CHANNEL_TXUSRCLK2_VAL (1'b0),
    .GTHE4_CHANNEL_TXUSRCLK_TIE_EN (1'b0),
    .GTHE4_CHANNEL_TXUSRCLK_VAL (1'b0),
    .GTHE4_CHANNEL_TX_CLK25_DIV (5),
    .GTHE4_CHANNEL_TX_CLK25_DIV (4),
    .GTHE4_CHANNEL_TX_CLKMUX_EN (1'b1),
    .GTHE4_CHANNEL_TX_DATA_WIDTH (20),
    .GTHE4_CHANNEL_TX_DCC_LOOP_RST_CFG (16'b0000000000000100),
    ......
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_ooc.xdc
    View file @ 7621f92c
    ......@@ -57,7 +57,7 @@
    create_clock -period 16.0 [get_ports gtwiz_reset_clk_freerun_in]
    # CPLL reference clock constraint (will be overridden by required constraint on IBUFDS_GTE4 input in context)
    create_clock -period 8.0 [get_ports gtrefclk0_in[0]]
    create_clock -period 10.0 [get_ports gtrefclk0_in[0]]
    # DRP clock constraint for CHANNEL primitive
    create_clock -period 16.0 [get_ports drpclk_in[0]]
    ......
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