wr_minic: added testbench (interfaced via 2 cascaded WR Endpoints)

7c852bf7 · Tomasz Wlostowski · 9750bc52 · 7c852bf7 · 7c852bf7 · 7c852bf7
Commit 7c852bf7 authored Oct 25, 2011 by Tomasz Wlostowski
5 changed files
--- a/testbench/wr_minic_with_ep/Manifest.py
+++ b/testbench/wr_minic_with_ep/Manifest.py
+action = "simulation"
+files = "main.sv"
+#fetchto = "../../ip_cores"
+
+vlog_opt="+incdir+../../sim"
+
+modules ={"local" : ["../../ip_cores/general-cores",
+                     "../../modules/wr_endpoint", 
+                     "../../modules/wr_mini_nic" ] };
--- a/testbench/wr_minic_with_ep/ep2ep_wrapper.svh
+++ b/testbench/wr_minic_with_ep/ep2ep_wrapper.svh
+
+`include "endpoint_regs.v"
+`include "endpoint_mdio.v"
+
+interface ITXTSU_Bus;
+
+
+   logic valid;
+   logic ack;
+   logic [4:0] port_id;
+   logic [15:0] frame_id;
+   logic [31:0] ts;
+
+   modport endpoint
+     (
+      input ack,
+      output valid,
+      output port_id,
+      output frame_id,
+      output ts
+      );
+
+   modport nic
+     (
+      output ack,
+      input valid,
+      input port_id,
+      input frame_id,
+      input ts
+      );
+endinterface // txtsu_if
+
+`define EP_QMODE_ACCESS 0
+`define EP_QMODE_TRUNK 1
+`define EP_QMODE_UNQ 3
+`define EP_QMODE_VLAN_DISABLED 2
+
+module ep2ep_wrapper
+  (
+   input clk_sys_i,
+   input clk_ref_i,
+   input rst_n_i,
+
+   IWishboneSlave.slave src_a,
+   IWishboneMaster.master snk_a,
+
+   IWishboneLink.slave src_b,
+   IWishboneLink.master snk_b,
+   
+   ITXTSU_Bus.endpoint txts_a,
+   ITXTSU_Bus.endpoint txts_b
+  );
+
+
+   wire[15:0] gtx_data;
+   wire [1:0]gtx_k;
+   wire gtx_disparity;
+   wire gtx_enc_error;
+   wire [15:0] grx_data;
+   wire grx_clk;
+   wire [1:0]grx_k;
+   wire grx_enc_error;
+   wire [3:0] grx_bitslide;
+   wire gtp_rst;
+   wire tx_clock;
+
+   IWishboneMaster 
+     #(
+       .g_data_width(32),
+       .g_addr_width(32))
+   sys_a
+     (
+      .clk_i(clk_sys_i),
+      .rst_n_i(rst_n_i)
+      );
+
+   IWishboneMaster 
+     #(
+       .g_data_width(32),
+       .g_addr_width(32))
+   sys_b
+     (
+      .clk_i(clk_sys_i),
+      .rst_n_i(rst_n_i)
+      );
+
+   
+   wr_endpoint
+     #(
+       .g_simulation          (1),
+       .g_pcs_16bit(0),
+       .g_rx_buffer_size (1024),
+       .g_with_rx_buffer(1),
+       .g_with_timestamper    (1),
+       .g_with_dpi_classifier (0),
+       .g_with_vlans          (0),
+       .g_with_rtu            (0)
+      ) EP_A (
+              .clk_ref_i (clk_ref_i),
+              .clk_sys_i (clk_sys_i),
+              .rst_n_i  (rst_n_i),
+              .pps_csync_p1_i (1'b0),
+
+              .phy_rst_o   (),
+              .phy_loopen_o (),
+              .phy_enable_o (),
+              .phy_syncen_o (),
+
+              .phy_ref_clk_i      (clk_ref_i),
+              .phy_tx_data_o      (gtx_data),
+              .phy_tx_k_o         (gtx_k),
+              .phy_tx_disparity_i (1'b1),
+              .phy_tx_enc_err_i   (1'b0),
+
+              .phy_rx_data_i     (grx_data),
+              .phy_rx_clk_i      (clk_ref_i),
+              .phy_rx_k_i        (grx_k),
+              .phy_rx_enc_err_i  (1'b0),
+              .phy_rx_bitslide_i (5'b0),
+
+              .src_dat_o   (src_a.dat_i),
+              .src_adr_o   (src_a.adr),
+              .src_sel_o   (src_a.sel),
+              .src_cyc_o   (src_a.cyc),
+              .src_stb_o   (src_a.stb),
+              .src_we_o    (src_a.we),
+              .src_stall_i (src_a.stall),
+              .src_ack_i   (src_a.ack),
+
+              .snk_dat_i   (snk_a.dat_o[15:0]),
+              .snk_adr_i   (snk_a.adr[1:0]),
+              .snk_sel_i   (snk_a.sel[1:0]),
+              .snk_cyc_i   (snk_a.cyc),
+              .snk_stb_i   (snk_a.stb),
+              .snk_we_i    (snk_a.we),
+              .snk_stall_o (snk_a.stall),
+              .snk_ack_o   (snk_a.ack),
+              .snk_err_o   (snk_a.err),
+              .snk_rty_o   (snk_a.rty),
+
+              .txtsu_port_id_o (txts_a.port_id),
+              .txtsu_frame_id_o (txts_a.frame_id),
+              .txtsu_tsval_o (txts_a.ts),
+              .txtsu_valid_o (txts_a.valid),
+              .txtsu_ack_i (txts_a.ack),
+
+              .rtu_full_i (1'b0),
+              .rtu_almost_full_i (1'b0),
+
+              .wb_cyc_i(sys_a.cyc),
+              .wb_stb_i (sys_a.stb),
+              .wb_we_i (sys_a.we),
+              .wb_sel_i(sys_a.sel),
+              .wb_adr_i(sys_a.adr[7:0]),
+              .wb_dat_i(sys_a.dat_o),
+              .wb_dat_o(sys_a.dat_i),
+              .wb_ack_o (sys_a.ack)
+    );
+
+
+      wr_endpoint
+     #(
+       .g_simulation          (1),
+       .g_pcs_16bit(0),
+       .g_rx_buffer_size (1024),
+       .g_with_rx_buffer(1),
+       .g_with_timestamper    (1),
+       .g_with_dpi_classifier (0),
+       .g_with_vlans          (0),
+       .g_with_rtu            (0)
+      ) EP_B (
+              .clk_ref_i (clk_ref_i),
+              .clk_sys_i (clk_sys_i),
+              .rst_n_i  (rst_n_i),
+              .pps_csync_p1_i (1'b0),
+
+              .phy_rst_o   (),
+              .phy_loopen_o (),
+              .phy_enable_o (),
+              .phy_syncen_o (),
+
+              .phy_ref_clk_i      (clk_ref_i),
+              .phy_tx_data_o      (grx_data),
+              .phy_tx_k_o         (grx_k),
+              .phy_tx_disparity_i (1'b1),
+              .phy_tx_enc_err_i   (1'b0),
+
+              .phy_rx_data_i     (gtx_data),
+              .phy_rx_clk_i      (clk_ref_i),
+              .phy_rx_k_i        (gtx_k),
+              .phy_rx_enc_err_i  (1'b0),
+              .phy_rx_bitslide_i (5'b0),
+
+              .src_dat_o   (src_b.dat_i),
+              .src_adr_o   (src_b.adr),
+              .src_sel_o   (src_b.sel),
+              .src_cyc_o   (src_b.cyc),
+              .src_stb_o   (src_b.stb),
+              .src_we_o    (src_b.we),
+              .src_stall_i (src_b.stall),
+              .src_ack_i   (src_b.ack),
+
+              .snk_dat_i   (snk_b.dat_i[15:0]),
+              .snk_adr_i   (snk_b.adr[1:0]),
+              .snk_sel_i   (snk_b.sel[1:0]),
+              .snk_cyc_i   (snk_b.cyc),
+              .snk_stb_i   (snk_b.stb),
+              .snk_we_i    (snk_b.we),
+              .snk_stall_o (snk_b.stall),
+              .snk_ack_o   (snk_b.ack),
+              .snk_err_o   (snk_b.err),
+              .snk_rty_o   (snk_b.rty),
+
+              .txtsu_port_id_o (txts_b.port_id),
+              .txtsu_frame_id_o (txts_b.frame_id),
+              .txtsu_tsval_o (txts_b.ts),
+              .txtsu_valid_o (txts_b.valid),
+              .txtsu_ack_i (txts_b.ack),
+
+              .rtu_full_i (1'b0),
+              .rtu_almost_full_i (1'b0),
+
+              .wb_cyc_i(sys_b.cyc),
+              .wb_stb_i (sys_b.stb),
+              .wb_we_i (sys_b.we),
+              .wb_sel_i(sys_b.sel),
+              .wb_adr_i(sys_b.adr[7:0]),
+              .wb_dat_i(sys_b.dat_o),
+              .wb_dat_o(sys_b.dat_i),
+              .wb_ack_o (sys_b.ack)
+    );
+
+   task ep_init(CWishboneAccessor acc);
+      acc.set_mode(CLASSIC);
+      acc.write(`ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN);
+      acc.write(`ADDR_EP_RFCR, 1518 << `EP_RFCR_MRU_OFFSET);
+      acc.write(`ADDR_EP_VCR0, `EP_QMODE_VLAN_DISABLED << `EP_VCR0_QMODE_OFFSET);
+      acc.write(`ADDR_EP_TSCR, `EP_TSCR_EN_RXTS);
+   endtask // ep_init
+
+   initial begin
+      while(!rst_n_i)
+        @(posedge clk_sys_i);
+      #1us;
+      
+      $display("InitEndpoints");
+      
+      
+      ep_init(sys_a.get_accessor());
+      ep_init(sys_b.get_accessor());
+
+      
+   end
+   
+
+endmodule // endpoint_phy_wrapper
\ No newline at end of file
--- a/testbench/wr_minic_with_ep/main.sv
+++ b/testbench/wr_minic_with_ep/main.sv
+`include "if_wb_master.svh"
+`include "if_wb_slave.svh"
+`include "if_wb_link.svh"
+`include "wb_packet_source.svh"
+`include "wb_packet_sink.svh"
+
+`include "drivers/simdrv_minic.svh"
+`include "ep2ep_wrapper.svh"
+
+
+module main;
+
+   reg clk_ref  = 1'b0;
+   reg clk_sys  = 1'b0;
+   
+   reg rst_n    = 1'b0;
+
+   always #4ns clk_ref <= ~clk_ref;
+   always@(posedge clk_ref) clk_sys <= ~clk_sys;
+
+   
+   initial begin
+      repeat(3) @(posedge clk_sys);
+      rst_n <= 1'b1;
+   end
+
+   IWishboneMaster 
+     #(
+       .g_data_width(16),
+       .g_addr_width(2))
+   U_wrf_source
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+
+   IWishboneSlave
+     #(
+       .g_data_width(16),
+       .g_addr_width(2))
+   U_wrf_sink
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+   
+   IWishboneMaster 
+     #(
+       .g_data_width(32),
+       .g_addr_width(32))
+   U_sys_bus_master
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+
+
+   IWishboneMaster 
+     #(
+       .g_data_width(32),
+       .g_addr_width(16))
+   U_pmem_bus_master
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+
+
+   
+   IWishboneLink #(16,2) ep2minic();
+   IWishboneLink #(16,2) minic2ep();
+
+   ITXTSU_Bus dummy();
+   ITXTSU_Bus minic_ts();
+   
+   
+   ep2ep_wrapper U_Eps
+     (
+      .clk_sys_i(clk_sys),
+      .clk_ref_i(clk_ref),
+      .rst_n_i(rst_n),
+      .snk_a(U_wrf_source.master),
+      .src_a(U_wrf_sink.slave),
+      .snk_b(minic2ep.master),
+      .src_b(ep2minic.slave),
+      .txts_a(dummy.endpoint),
+      .txts_b(minic_ts.endpoint)
+      );
+   
+
+   wire minic_irq;
+   wire [31:0] pmem_wr_data, pmem_rd_data;
+   wire [13:0] pmem_addr;
+   wire pmem_wr;
+   
+   wr_mini_nic DUT 
+     (
+      .clk_sys_i (clk_sys),
+      .rst_n_i   (rst_n),
+
+      .mem_data_o (pmem_wr_data),
+      .mem_addr_o (pmem_addr),
+      .mem_data_i (pmem_rd_data),
+      .mem_wr_o   (pmem_wr),
+
+      .src_dat_o  (minic2ep.slave.dat_i),
+      .src_adr_o  (minic2ep.slave.adr),
+      .src_sel_o  (minic2ep.slave.sel),
+      .src_cyc_o  (minic2ep.slave.cyc),
+      .src_stb_o  (minic2ep.slave.stb),
+      .src_we_o   (minic2ep.slave.we),
+      .src_stall_i(minic2ep.slave.stall),
+      .src_err_i  (minic2ep.slave.err),
+      .src_ack_i  (minic2ep.slave.ack),
+
+      .snk_dat_i  (ep2minic.master.dat_o), 
+      .snk_adr_i  (ep2minic.master.adr),
+      .snk_sel_i  (ep2minic.master.sel),
+      .snk_cyc_i  (ep2minic.master.cyc),
+      .snk_stb_i  (ep2minic.master.stb), 
+      .snk_we_i    (ep2minic.master.we),
+      .snk_stall_o (ep2minic.master.stall),
+      .snk_err_o   (ep2minic.master.err),
+      .snk_ack_o   (ep2minic.master.ack),
+
+      .txtsu_port_id_i  (5'b0),
+      .txtsu_frame_id_i (16'b0),
+      .txtsu_tsval_i   (32'b0),
+      .txtsu_valid_i   (1'b0),
+      .txtsu_ack_o     (),
+
+
+      .wb_cyc_i   (U_sys_bus_master.cyc),
+      .wb_stb_i   (U_sys_bus_master.stb),
+      .wb_we_i    (U_sys_bus_master.we),
+      .wb_sel_i   (U_sys_bus_master.sel),
+      .wb_adr_i   (U_sys_bus_master.adr),
+      .wb_dat_i   (U_sys_bus_master.dat_o),
+      .wb_dat_o   (U_sys_bus_master.dat_i),
+      .wb_ack_o   (U_sys_bus_master.ack),
+      .wb_stall_o (U_sys_bus_master.stall),
+      .wb_irq_o   (minic_irq)
+      );
+
+   minic_packet_buffer PBUF
+     (
+      .clk_sys_i (clk_sys),
+      .rst_n_i  (rst_n),
+
+      .minic_addr_i (pmem_addr),
+      .minic_data_i (pmem_wr_data),
+      .minic_wr_i   (pmem_wr),
+      .minic_data_o (pmem_rd_data),
+      
+      .wb_cyc_i   (U_pmem_bus_master.cyc),
+      .wb_stb_i   (U_pmem_bus_master.stb),
+      .wb_we_i    (U_pmem_bus_master.we),
+      .wb_addr_i   (U_pmem_bus_master.adr[13:0]),
+      .wb_data_i   (U_pmem_bus_master.dat_o),
+      .wb_data_o   (U_pmem_bus_master.dat_i),
+      .wb_ack_o   (U_pmem_bus_master.ack)
+    );
+
+   
+   CSimDrv_Minic minic;
+
+
+
+   task test_tx_path(int n_packets, CSimDrv_Minic minic, WBPacketSink sink);
+      EthPacketGenerator gen = new;
+      EthPacket pkt, tmpl;
+      EthPacket txed[$];
+      int i;
+
+       tmpl           = new;
+      tmpl.src       = '{1,2,3,4,5,6};
+      tmpl.dst       = '{10,11,12,13,14,15};
+      tmpl.has_smac  = 1;
+      tmpl.is_q      = 0;
+      
+      gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE | EthPacketGenerator::TX_OOB | EthPacketGenerator::EVEN_LENGTH) ;
+      gen.set_template(tmpl);
+      gen.set_size(60,1500);
+      
+      for(i=0;i<n_packets;i++)
+        begin
+           pkt  = gen.gen();
+           minic.send(pkt);
+           txed.push_back(pkt);
+        end
+
+      fork
+         forever
+           begin
+              minic.run();
+              #1;
+           end
+
+         forever
+           begin
+            if(sink.poll())
+              begin
+                 EthPacket rxp, sent;
+                 sink.recv(rxp);
+                 sent  = txed.pop_front();
+                 if(!sent.equal(rxp))
+                   begin
+                      sent.dump();
+                      rxp.dump();
+                      $stop;
+                   end
+              end
+              #1;
+         end
+      join
+
+   endtask
+   
+   
+   
+   initial begin
+      CWishboneAccessor sys_bus, pmem_bus;     
+      WBPacketSource src  = new(U_wrf_source.get_accessor());
+      WBPacketSink sink   = new(U_wrf_sink.get_accessor()); 
+      EthPacketGenerator gen = new;
+      EthPacket pkt, tmpl;
+      EthPacket txed[$];
+      int i;
+
+    
+      
+
+   
+      
+      
+      @(posedge rst_n);
+      @(posedge clk_sys);
+ 
+      sys_bus                                 = U_sys_bus_master.get_accessor();
+      sys_bus.set_mode(CLASSIC);
+      pmem_bus                                 = U_pmem_bus_master.get_accessor();
+      pmem_bus.set_mode(CLASSIC);
+
+      minic  = new('h10000, sys_bus, 0, pmem_bus, 0);
+      minic.init();
+
+
+      test_tx_path(10000, minic, sink);
+      
+
+/* -----\/----- EXCLUDED -----\/-----
+     
+         tmpl           = new;
+      tmpl.src       = '{1,2,3,4,5,6};
+      tmpl.dst       = '{10,11,12,13,14,15};
+      tmpl.has_smac  = 1;
+      tmpl.is_q      = 0;
+      
+      gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /-*| EthPacketGenerator::RX_OOB*-/) ;
+      gen.set_template(tmpl);
+      gen.set_size(60,1500);
+
+
+      fork
+         forever
+           begin
+              minic.run();
+      
+
+              if(minic.poll())
+              begin
+                 EthPacket rxp, sent;
+                 minic.recv(rxp);
+                 sent  = txed.pop_front();
+                 if(!sent.equal(rxp, EthPacket::CMP_OOB))
+                   begin
+                      sent.dump();
+                      rxp.dump();
+                      $stop;
+                   end
+
+                 
+              end
+
+              #1;
+              end
+
+//         forever
+           begin
+              for(i=0;i<100;i++)
+                begin
+                   pkt  = gen.gen();
+                   src.send(pkt);
+                   txed.push_back(pkt);
+                end
+
+              
+           end
+         
+    //          #1;
+              
+  //         end // forever begin
+
+         
+         
+         
+              
+
+      join      
+
+         
+      
+        
+      
+ -----/\----- EXCLUDED -----/\----- */
+   end // initial begin
+
+   
+   
+endmodule // main
+
+
+
--- a/testbench/wr_minic_with_ep/run.do
+++ b/testbench/wr_minic_with_ep/run.do
+vlog -sv main.sv +incdir+"." +incdir+../../sim
+make -f Makefile
+vsim -L unisim -t 10fs work.main -voptargs="+acc"
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 250us
+wave zoomfull
+radix -hexadecimal
--- a/testbench/wr_minic_with_ep/wave.do
+++ b/testbench/wr_minic_with_ep/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/minic2ep/g_data_width
+add wave -noupdate /main/minic2ep/g_addr_width
+add wave -noupdate /main/minic2ep/adr
+add wave -noupdate /main/minic2ep/dat_o
+add wave -noupdate /main/minic2ep/dat_i
+add wave -noupdate /main/minic2ep/sel
+add wave -noupdate /main/minic2ep/ack
+add wave -noupdate /main/minic2ep/stall
+add wave -noupdate /main/minic2ep/err
+add wave -noupdate /main/minic2ep/rty
+add wave -noupdate /main/minic2ep/cyc
+add wave -noupdate /main/minic2ep/stb
+add wave -noupdate /main/minic2ep/we
+add wave -noupdate -divider sink
+add wave -noupdate /main/U_wrf_sink/g_addr_width
+add wave -noupdate /main/U_wrf_sink/g_data_width
+add wave -noupdate /main/U_wrf_sink/clk_i
+add wave -noupdate /main/U_wrf_sink/rst_n_i
+add wave -noupdate /main/U_wrf_sink/adr
+add wave -noupdate /main/U_wrf_sink/dat_i
+add wave -noupdate /main/U_wrf_sink/sel
+add wave -noupdate /main/U_wrf_sink/dat_o
+add wave -noupdate /main/U_wrf_sink/ack
+add wave -noupdate /main/U_wrf_sink/stall
+add wave -noupdate /main/U_wrf_sink/err
+add wave -noupdate /main/U_wrf_sink/rty
+add wave -noupdate /main/U_wrf_sink/cyc
+add wave -noupdate /main/U_wrf_sink/stb
+add wave -noupdate /main/U_wrf_sink/we
+add wave -noupdate /main/U_wrf_sink/last_access_t
+add wave -noupdate /main/U_wrf_sink/cyc_prev
+add wave -noupdate /main/U_wrf_sink/trans_index
+add wave -noupdate /main/U_wrf_sink/first_transaction
+add wave -noupdate /main/U_wrf_sink/settings
+add wave -noupdate /main/U_wrf_sink/cyc_start
+add wave -noupdate /main/U_wrf_sink/cyc_end
+add wave -noupdate /main/U_wrf_sink/clk_i
+add wave -noupdate /main/U_wrf_sink/rst_n_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_vlans
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_dpi_classifier
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_rtu
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_rx_buffer
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_rx_buffer_size
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/clk_sys_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/clk_rx_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rst_n_sys_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rst_n_rx_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_fab_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_fifo_almostfull_o
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_busy_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/src_wb_o
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/src_wb_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fc_pause_p_o
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fc_pause_delay_o
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fc_buffer_occupation_o
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rmon_o
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/regs_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rtu_rq_o
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rtu_full_i
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rtu_rq_valid_o
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/state
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/gap_cntr
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/counter
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rxdata_saved
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/next_hdr
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/is_pause
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/data_firstword
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/flush_stall
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/stb_int
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fab_int
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/dreq_int
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ack_count
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/src_out_int
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/tmp_sel
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/tmp_dat
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fab_pipe
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/dreq_pipe
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_done
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_is_hp
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_is_pause
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_pause_quanta
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pfilter_pclass
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pfilter_drop
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pfilter_done
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/vlan_tclass
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/vlan_vid
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/vlan_tag_done
+add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_fifo_almostfull
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {62482422150 fs} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {54279296390 fs} {70685547910 fs}