platform/xilinx: adding rdy_o to gtx and gtp wrappers to indicate when serdes is…

platform/xilinx: adding rdy_o to gtx and gtp wrappers to indicate when serdes is ready and produces rx clock

platform/xilinx: adding rdy_o to gtx and gtp wrappers to indicate when serdes is…
platform/xilinx: adding rdy_o to gtx and gtp wrappers to indicate when serdes is ready and produces rx clock
7d1b3def · Grzegorz Daniluk · 8102d8cf · 7d1b3def · 7d1b3def · 7d1b3def
Commit 7d1b3def authored Mar 02, 2015 by Grzegorz Daniluk
3 changed files
--- a/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
@@ -110,6 +110,9 @@ entity wr_gtp_phy_spartan6 is
    -- local loopback enable (Tx->Rx), active hi
    ch0_loopen_i : in std_logic;

+    -- gtp0 ready: locked & aligned
+    ch0_rdy_o : out std_logic;
+
 -- Port 1
    ch1_ref_clk_i : in std_logic;

@@ -126,6 +129,7 @@ entity wr_gtp_phy_spartan6 is

    ch1_rst_i    : in std_logic := '0';
    ch1_loopen_i : in std_logic := '0';
+    ch1_rdy_o    : out std_logic;

 -- Serial I/O

@@ -529,6 +533,8 @@ begin  -- rtl

 -- drive the recovered clock output
    ch0_rx_rbclk_o <= ch0_rx_rec_clk;
+    -- drive ch0 ready indicator as well
+    ch0_rdy_o <= ch0_rx_enable_output_synced;

  end generate gen_with_channel0;

@@ -682,6 +688,7 @@ begin  -- rtl
    end process;

    ch1_rx_rbclk_o <= ch1_rx_rec_clk;
+    ch1_rdy_o <= ch1_rx_enable_output_synced;
  end generate gen_with_channel1;



--- a/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
@@ -109,11 +109,9 @@ entity wr_gtx_phy_kintex7 is
    pad_txp_o : out std_logic;

    pad_rxn_i : in std_logic := '0';
-    pad_rxp_i : in std_logic := '0'
-
-    );
-
+    pad_rxp_i : in std_logic := '0';

+    rdy_o     : out std_logic);
 end wr_gtx_phy_kintex7;

 architecture rtl of wr_gtx_phy_kintex7 is
@@ -440,6 +438,7 @@ U_GTX_INST : WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT
  rst_done_n       <= not rst_done;
  pll_lockdet      <= txpll_lockdet and rxpll_lockdet;
  everything_ready <= rst_done and pll_lockdet;
+  rdy_o            <= everything_ready;

  trig2(3) <= rx_rst_done;
  trig2(4) <= tx_rst_done;

--- a/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
@@ -111,7 +111,9 @@ entity wr_gtx_phy_virtex6 is
    pad_txp_o : out std_logic;

    pad_rxn_i : in std_logic := '0';
-    pad_rxp_i : in std_logic := '0'
+    pad_rxp_i : in std_logic := '0';
+    
+    rdy_o : out std_logic

    );

@@ -403,6 +405,7 @@ begin  -- rtl
  serdes_ready     <= rst_done and pll_lockdet;
  align_enable     <= serdes_ready;
  everything_ready <= serdes_ready and align_done;
+  rdy_o <= everything_ready;

  trig2(3) <= rx_rst_done;
  trig2(4) <= tx_rst_done;