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White Rabbit core collection
Commit 7ede53fb authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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eca: prevent inference of taps

parent 1ba57663
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modules/wr_eca/eca.vhd
View file @ 7ede53fb
......@@ -43,6 +43,9 @@ entity eca is
end eca;
architecture rtl of eca is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_num_channels : natural := g_channel_types'length;
constant c_channel_bits : natural := f_eca_log2(c_num_channels+1);
......
modules/wr_eca/eca_bitonic.vhd
View file @ 7ede53fb
......@@ -42,6 +42,9 @@ entity eca_bitonic is
end eca_bitonic;
architecture rtl of eca_bitonic is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
begin
-- Handle the case of only a single number = pass-through
......
modules/wr_eca/eca_bitonic_helper.vhd
View file @ 7ede53fb
......@@ -42,6 +42,10 @@ entity eca_bitonic_helper is
end eca_bitonic_helper;
architecture rtl of eca_bitonic_helper is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_log_size1 : natural := g_log_size - 1;
constant c_full : natural := 2**g_log_size;
constant c_half : natural := 2**c_log_size1;
......
modules/wr_eca/eca_bitonic_swap.vhd
View file @ 7ede53fb
......@@ -43,6 +43,9 @@ entity eca_bitonic_swap is
end eca_bitonic_swap;
architecture rtl of eca_bitonic_swap is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
signal r_a, r_b : std_logic_vector(g_wide-1 downto 0) := (others => '0');
signal s_flip : boolean;
......
modules/wr_eca/eca_bitonic_tb.vhd
View file @ 7ede53fb
......@@ -36,6 +36,9 @@ entity eca_bitonic_tb is
end eca_bitonic_tb;
architecture rtl of eca_bitonic_tb is
-- Out of principle, tell quartus to leave my design alone.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_size : natural := g_case;
constant c_full : natural := 2**c_size;
......
modules/wr_eca/eca_channel.vhd
View file @ 7ede53fb
......@@ -102,6 +102,9 @@ entity eca_channel is
end eca_channel;
architecture rtl of eca_channel is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_count_bits : natural := g_log_counter;
constant c_valid_bits : natural := f_eca_log2_min1(g_num_channels);
......
modules/wr_eca/eca_compact.vhd
View file @ 7ede53fb
......@@ -44,6 +44,9 @@ entity eca_compact is
end eca_compact;
architecture rtl of eca_compact is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
-- result(i) := xor_{j in 0 to i} x(j)
-- latency O(log n), area = O(n)
......
modules/wr_eca/eca_data.vhd
View file @ 7ede53fb
......@@ -42,6 +42,9 @@ entity eca_data is
end eca_data;
architecture rtl of eca_data is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_conflict : natural := 0;
constant c_late : natural := c_conflict+1;
......
modules/wr_eca/eca_fifo.vhd
View file @ 7ede53fb
......@@ -46,6 +46,9 @@ entity eca_fifo is
end eca_fifo;
architecture rtl of eca_fifo is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_low : unsigned(g_log_size-1 downto 0) := (others => '0');
constant c_high : unsigned(g_log_size downto 0) := '1' & c_low;
......
modules/wr_eca/eca_free.vhd
View file @ 7ede53fb
......@@ -43,6 +43,9 @@ entity eca_free is
end eca_free;
architecture rtl of eca_free is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_zero : std_logic_vector(g_log_size-1 downto 0) := (others => '0');
......
modules/wr_eca/eca_msi.vhd
View file @ 7ede53fb
......@@ -55,6 +55,9 @@ entity eca_msi is
end eca_msi;
architecture rtl of eca_msi is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_chan_bits : natural := f_eca_log2(g_num_channels);
constant c_zero : std_logic_vector(g_num_channels-1 downto 0) := (others => '0');
......
modules/wr_eca/eca_piso_fifo.vhd
View file @ 7ede53fb
......@@ -45,6 +45,9 @@ entity eca_piso_fifo is
end eca_piso_fifo;
architecture rtl of eca_piso_fifo is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
-- Deal with a fifo smaller than it is wide by rounding up
function f_sub_min1(x, y : natural) return natural is
......
modules/wr_eca/eca_queue.vhd
View file @ 7ede53fb
......@@ -46,6 +46,9 @@ entity eca_queue is
end eca_queue;
architecture rtl of eca_queue is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
signal ra_pop_xor : std_logic_vector(5 downto 0) := (others => '0');
signal sa_pop : std_logic;
......
modules/wr_eca/eca_rmw.vhd
View file @ 7ede53fb
......@@ -62,6 +62,9 @@ end eca_rmw;
-- A0-read, A0-write, B0-read, B0-write, B1-read, B1-write
architecture rtl of eca_rmw is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
signal s_q0_addr : std_logic_vector(g_addr_bits-1 downto 0);
signal s_q1_addr : std_logic_vector(g_addr_bits-1 downto 0);
......
modules/wr_eca/eca_scan.vhd
View file @ 7ede53fb
......@@ -59,6 +59,9 @@ entity eca_scan is
end eca_scan;
architecture rtl of eca_scan is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_log_count : natural := g_log_max_delay - g_log_latency;
constant c_multiplier1_bits : std_logic_vector(g_log_multiplier downto 0) := (others => '0');
......
modules/wr_eca/eca_sdp.vhd
View file @ 7ede53fb
......@@ -49,6 +49,9 @@ entity eca_sdp is
end eca_sdp;
architecture rtl of eca_sdp is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_depth : natural := 2**g_addr_bits;
......
modules/wr_eca/eca_tag_channel.vhd
View file @ 7ede53fb
......@@ -63,6 +63,9 @@ entity eca_tag_channel is
end eca_tag_channel;
architecture rtl of eca_tag_channel is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_log_channels : natural := f_eca_log2(g_num_channels);
constant c_log_cal_size : natural := g_log_latency - g_log_multiplier;
......
modules/wr_eca/eca_tdp.vhd
View file @ 7ede53fb
......@@ -49,6 +49,9 @@ entity eca_tdp is
end eca_tdp;
architecture rtl of eca_tdp is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_depth : natural := 2**g_addr_bits;
......
modules/wr_eca/eca_tlu.vhd
View file @ 7ede53fb
......@@ -49,6 +49,9 @@ entity eca_tlu is
end eca_tlu;
architecture rtl of eca_tlu is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_serdes : natural := 8;
constant c_input_bits : natural := f_eca_log2(g_inputs);
......
modules/wr_eca/eca_tlu_fsm.vhd
View file @ 7ede53fb
......@@ -46,6 +46,9 @@ entity eca_tlu_fsm is
end eca_tlu_fsm;
architecture rtl of eca_tlu_fsm is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
constant c_increment_bits : natural := f_eca_log2(g_serdes+1);
constant c_history_bits : natural := f_eca_log2(g_history);
......
modules/wr_eca/wr_eca.vhd
View file @ 7ede53fb
......@@ -66,6 +66,9 @@ entity wr_eca is
end wr_eca;
architecture rtl of wr_eca is
-- Quartus 11+ goes crazy and infers 7 M9Ks in an altshift_taps! Stop it.
attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
signal sa_time : t_time;
signal sa_io : t_eca_matrix(g_num_ios-1 downto 0, 7 downto 0);
......
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