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White Rabbit core collection
Commit 7f7f0255 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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added mode to test pck inj_gen: corrupting frames

parent a5e699c2
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Showing with 91 additions and 35 deletions
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 7f7f0255
......@@ -334,6 +334,7 @@ package endpoint_private_pkg is
inject_ready_o : out std_logic;
inject_packet_sel_i : in std_logic_vector(2 downto 0);
inject_user_value_i : in std_logic_vector(15 downto 0);
inject_mode_i : in std_logic_vector(1 downto 0);
mem_addr_o : out std_logic_vector(9 downto 0);
mem_data_i : in std_logic_vector(17 downto 0));
end component;
......@@ -395,6 +396,7 @@ package endpoint_private_pkg is
inject_packet_sel_o : out std_logic_vector(2 downto 0);
inject_user_value_o : out std_logic_vector(15 downto 0);
inject_ctr_ena_o : out std_logic;
inject_ctr_mode_o : out std_logic_vector(1 downto 0);
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers);
end component;
......
modules/wr_endpoint/ep_registers_pkg.vhd
View file @ 7f7f0255
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Thu Jan 16 14:57:37 2014
-- Created : Thu Jan 30 17:57:04 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -37,7 +37,8 @@ package ep_wbgen2_pkg is
dmsr_ps_rdy_i : std_logic;
inj_ctrl_pic_conf_ifg_i : std_logic_vector(15 downto 0);
inj_ctrl_pic_conf_sel_i : std_logic_vector(2 downto 0);
inj_ctrl_pic_valid_i : std_logic;
inj_ctrl_pic_conf_mode_i : std_logic_vector(2 downto 0);
inj_ctrl_pic_conf_valid_i : std_logic;
inj_ctrl_pic_ena_i : std_logic;
end record;
......@@ -59,7 +60,8 @@ package ep_wbgen2_pkg is
dmsr_ps_rdy_i => '0',
inj_ctrl_pic_conf_ifg_i => (others => '0'),
inj_ctrl_pic_conf_sel_i => (others => '0'),
inj_ctrl_pic_valid_i => '0',
inj_ctrl_pic_conf_mode_i => (others => '0'),
inj_ctrl_pic_conf_valid_i => '0',
inj_ctrl_pic_ena_i => '0'
);
......@@ -124,8 +126,10 @@ package ep_wbgen2_pkg is
inj_ctrl_pic_conf_ifg_load_o : std_logic;
inj_ctrl_pic_conf_sel_o : std_logic_vector(2 downto 0);
inj_ctrl_pic_conf_sel_load_o : std_logic;
inj_ctrl_pic_valid_o : std_logic;
inj_ctrl_pic_valid_load_o : std_logic;
inj_ctrl_pic_conf_mode_o : std_logic_vector(2 downto 0);
inj_ctrl_pic_conf_mode_load_o : std_logic;
inj_ctrl_pic_conf_valid_o : std_logic;
inj_ctrl_pic_conf_valid_load_o : std_logic;
inj_ctrl_pic_ena_o : std_logic;
inj_ctrl_pic_ena_load_o : std_logic;
end record;
......@@ -189,8 +193,10 @@ package ep_wbgen2_pkg is
inj_ctrl_pic_conf_ifg_load_o => '0',
inj_ctrl_pic_conf_sel_o => (others => '0'),
inj_ctrl_pic_conf_sel_load_o => '0',
inj_ctrl_pic_valid_o => '0',
inj_ctrl_pic_valid_load_o => '0',
inj_ctrl_pic_conf_mode_o => (others => '0'),
inj_ctrl_pic_conf_mode_load_o => '0',
inj_ctrl_pic_conf_valid_o => '0',
inj_ctrl_pic_conf_valid_load_o => '0',
inj_ctrl_pic_ena_o => '0',
inj_ctrl_pic_ena_load_o => '0'
);
......@@ -240,7 +246,8 @@ tmp.dmsr_ps_val_i := f_x_to_zero(left.dmsr_ps_val_i) or f_x_to_zero(right.dmsr_p
tmp.dmsr_ps_rdy_i := f_x_to_zero(left.dmsr_ps_rdy_i) or f_x_to_zero(right.dmsr_ps_rdy_i);
tmp.inj_ctrl_pic_conf_ifg_i := f_x_to_zero(left.inj_ctrl_pic_conf_ifg_i) or f_x_to_zero(right.inj_ctrl_pic_conf_ifg_i);
tmp.inj_ctrl_pic_conf_sel_i := f_x_to_zero(left.inj_ctrl_pic_conf_sel_i) or f_x_to_zero(right.inj_ctrl_pic_conf_sel_i);
tmp.inj_ctrl_pic_valid_i := f_x_to_zero(left.inj_ctrl_pic_valid_i) or f_x_to_zero(right.inj_ctrl_pic_valid_i);
tmp.inj_ctrl_pic_conf_mode_i := f_x_to_zero(left.inj_ctrl_pic_conf_mode_i) or f_x_to_zero(right.inj_ctrl_pic_conf_mode_i);
tmp.inj_ctrl_pic_conf_valid_i := f_x_to_zero(left.inj_ctrl_pic_conf_valid_i) or f_x_to_zero(right.inj_ctrl_pic_conf_valid_i);
tmp.inj_ctrl_pic_ena_i := f_x_to_zero(left.inj_ctrl_pic_ena_i) or f_x_to_zero(right.inj_ctrl_pic_ena_i);
return tmp;
end function;
......
modules/wr_endpoint/ep_tx_inject_ctrl.vhd
View file @ 7f7f0255
......@@ -65,6 +65,7 @@ entity ep_tx_inject_ctrl is
inject_packet_sel_o : out std_logic_vector(2 downto 0);
inject_user_value_o : out std_logic_vector(15 downto 0);
inject_ctr_ena_o : out std_logic;
inject_ctr_mode_o : out std_logic_vector(1 downto 0);
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers
......@@ -91,6 +92,7 @@ architecture rtl of ep_tx_inject_ctrl is
signal if_gap_value : unsigned(15 downto 0);
signal pck_sel : std_logic_vector(2 downto 0);
signal gen_ena : std_logic;
signal inj_mode : std_logic_vector(1 downto 0);
signal if_gap_cnt : unsigned(15 downto 0);
signal frame_id_cnt : unsigned(15 downto 0);
......@@ -133,9 +135,10 @@ begin -- rtl
gen_ena <= '0';
else
if(regs_i.inj_ctrl_pic_ena_load_o = '1') then -- writing the register
if (regs_i.inj_ctrl_pic_valid_o = '1') then
if (regs_i.inj_ctrl_pic_conf_valid_o = '1') then
if_gap_value <= unsigned(regs_i.inj_ctrl_pic_conf_ifg_o);
pck_sel <= regs_i.inj_ctrl_pic_conf_sel_o;
inj_mode <= regs_i.inj_ctrl_pic_conf_mode_o(1 downto 0);
end if;
gen_ena <= regs_i.inj_ctrl_pic_ena_o;
end if;
......@@ -217,11 +220,13 @@ begin -- rtl
inject_user_value_o <= std_logic_vector(frame_id_cnt);
inject_packet_sel_o <= pck_sel;
inject_ctr_ena_o <= gen_ena;
inject_ctr_mode_o <= inj_mode;
snk_dreq_o <= src_dreq_i when (state = IDLE) else '1'; -- dev/null if gen
src_fab_o <= snk_fab_i when (state = IDLE) else src_fab_null;-- dev/null if gen
regs_o.inj_ctrl_pic_conf_ifg_i <= std_logic_vector(if_gap_value);
regs_o.inj_ctrl_pic_conf_sel_i <= pck_sel;
regs_o.inj_ctrl_pic_valid_i <= '0';
regs_o.inj_ctrl_pic_conf_valid_i <= '0';
regs_o.inj_ctrl_pic_ena_i <= gen_ena;
regs_o.inj_ctrl_pic_conf_mode_i<= '0' & inj_mode;
end rtl;
modules/wr_endpoint/ep_tx_packet_injection.vhd
View file @ 7f7f0255
......@@ -68,6 +68,11 @@ entity ep_tx_packet_injection is
inject_ready_o : out std_logic;
inject_packet_sel_i : in std_logic_vector(2 downto 0);
inject_user_value_i : in std_logic_vector(15 downto 0);
inject_mode_i : in std_logic_vector(1 downto 0);
-- 0 : default
-- 1 : corrupt
-- 2 : unused
-- 3 : unused
mem_addr_o : out std_logic_vector(9 downto 0);
mem_data_i : in std_logic_vector(17 downto 0)
......@@ -150,14 +155,16 @@ begin -- rtl
inj_src.sof <= '0';
inj_src.eof <= '0';
inj_src.dvalid <= '0';
first_word <= '0';
inj_src.error <= '0';
first_word <= '0';
else
case state is
when WAIT_IDLE =>
inj_src.sof <= '0';
inj_src.eof <= '0';
inj_src.dvalid <= '0';
no_template_error <='0';
inj_src.error <= '0';
no_template_error <= '0';
first_word <= '0';
if(inject_req_i = '1') then --ML: we make sure that we remember the packet_sel_i
......@@ -203,10 +210,16 @@ begin -- rtl
if(template_last = '1' and inj_src.dvalid = '1' and first_word = '0' and src_dreq_i = '1') then
inj_src.dvalid <= '0';
state <= EOF;
inj_src.eof <= '1';
if(inject_mode_i = "01") then
inj_src.error <= '1';
else
inj_src.eof <= '1';
end if;
end if;
when EOF =>
inj_src.eof <= '0';
inj_src.error <= '0';
if(src_dreq_i = '1') then
state <= WAIT_IDLE;
select_inject <= '0';
......@@ -219,7 +232,7 @@ begin -- rtl
-- inj_src.bytesel <= '0';
-- the last word cannot be user-defined as we use the user bit to indicate odd size
inj_src.bytesel <= template_user when (template_last = '1' and first_word = '0') else '0';
inj_src.error <= '0';
-- inj_src.error <= '0';
p_inj_src_data : process(template_user, inject_user_value_i, mem_data_i,template_last,first_word)
begin
......
modules/wr_endpoint/ep_tx_path.vhd
View file @ 7f7f0255
......@@ -157,12 +157,14 @@ architecture rtl of ep_tx_path is
signal inject_ready : std_logic;
signal inject_packet_sel : std_logic_vector(2 downto 0);
signal inject_user_value : std_logic_vector(15 downto 0);
signal inject_mode : std_logic_vector( 1 downto 0);
signal inj_ctr_req : std_logic;
signal inj_ctr_ready : std_logic;
signal inj_ctr_packet_sel : std_logic_vector(2 downto 0);
signal inj_ctr_user_value : std_logic_vector(15 downto 0);
signal inj_ctr_ena : std_logic;
signal inj_ctr_ena : std_logic;
signal inj_ctr_mode : std_logic_vector( 1 downto 0);
begin -- rtl
......@@ -226,6 +228,7 @@ begin -- rtl
inject_packet_sel_o => inj_ctr_packet_sel,
inject_user_value_o => inj_ctr_user_value,
inject_ctr_ena_o => inj_ctr_ena,
inject_ctr_mode_o => inj_ctr_mode,
regs_i => regs_i,
regs_o => regs_o);
end generate gen_with_inj_ctrl;
......@@ -233,6 +236,7 @@ begin -- rtl
inject_req <= inj_ctr_req when (inj_ctr_ena ='1') else inject_req_i;
inject_packet_sel <= inj_ctr_packet_sel when (inj_ctr_ena ='1') else inject_packet_sel_i;
inject_user_value <= inj_ctr_user_value when (inj_ctr_ena ='1') else inject_user_value_i;
inject_mode <= inj_ctr_mode when (inj_ctr_ena ='1') else "00";
inj_ctr_ready <= inject_ready;
inject_ready_o <= inject_ready;
......@@ -279,6 +283,7 @@ begin -- rtl
inject_ready_o => inject_ready,
inject_packet_sel_i => inject_packet_sel,
inject_user_value_i => inject_user_value,
inject_mode_i => inject_mode,
mem_addr_o => vlan_mem_addr,
mem_data_i => vlan_mem_data);
end generate gen_with_injection;
......
modules/wr_endpoint/ep_tx_vlan_unit.vhd
View file @ 7f7f0255
......@@ -33,6 +33,10 @@
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- FIXME: redo ram split between VLAN/PCK_INJ to use the unused 256 words and
-- enable storing full-size frame (now max is 1024 bits, if we add 2x256
-- bytes it will be exactly what we need) -> this requires chagnes in
-- HDL+SW+SV
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
......@@ -98,6 +102,10 @@ begin -- behavioral
vut_rd_vid <= snk_fab_i.data(11 downto 0);
-- FIXME:
-- ML: currently 256 words of the ram are not used and we don't have space to store
-- max size frame (max tempalte is 512x2bytes = 1024 bytes)
-- we can use the unused bytes, just that some changes to sw+hw are needed
mem_addr_muxed <= ("00" & vut_rd_vid(11 downto 4)) when state /= IDLE else inject_mem_addr_i;
U_Untagged_Set_RAM : generic_dpram
......
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @ 7f7f0255
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Thu Jan 16 14:57:37 2014
-- Created : Thu Jan 30 17:57:04 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -153,7 +153,8 @@ begin
regs_o.dmsr_ps_rdy_load_o <= '0';
regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
regs_o.inj_ctrl_pic_valid_load_o <= '0';
regs_o.inj_ctrl_pic_conf_mode_load_o <= '0';
regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
regs_o.inj_ctrl_pic_ena_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -176,7 +177,8 @@ begin
regs_o.dmsr_ps_rdy_load_o <= '0';
regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
regs_o.inj_ctrl_pic_valid_load_o <= '0';
regs_o.inj_ctrl_pic_conf_mode_load_o <= '0';
regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
regs_o.inj_ctrl_pic_ena_load_o <= '0';
ack_in_progress <= '0';
else
......@@ -198,7 +200,8 @@ begin
regs_o.dmsr_ps_rdy_load_o <= '0';
regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
regs_o.inj_ctrl_pic_valid_load_o <= '0';
regs_o.inj_ctrl_pic_conf_mode_load_o <= '0';
regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
regs_o.inj_ctrl_pic_ena_load_o <= '0';
end if;
else
......@@ -658,17 +661,16 @@ begin
if (wb_we_i = '1') then
regs_o.inj_ctrl_pic_conf_ifg_load_o <= '1';
regs_o.inj_ctrl_pic_conf_sel_load_o <= '1';
regs_o.inj_ctrl_pic_valid_load_o <= '1';
regs_o.inj_ctrl_pic_conf_mode_load_o <= '1';
regs_o.inj_ctrl_pic_conf_valid_load_o <= '1';
regs_o.inj_ctrl_pic_ena_load_o <= '1';
end if;
rddata_reg(15 downto 0) <= regs_i.inj_ctrl_pic_conf_ifg_i;
rddata_reg(18 downto 16) <= regs_i.inj_ctrl_pic_conf_sel_i;
rddata_reg(20) <= regs_i.inj_ctrl_pic_valid_i;
rddata_reg(21) <= regs_i.inj_ctrl_pic_ena_i;
rddata_reg(22 downto 20) <= regs_i.inj_ctrl_pic_conf_mode_i;
rddata_reg(23) <= regs_i.inj_ctrl_pic_conf_valid_i;
rddata_reg(24) <= regs_i.inj_ctrl_pic_ena_i;
rddata_reg(19) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
......@@ -850,10 +852,12 @@ begin
regs_o.inj_ctrl_pic_conf_ifg_o <= wrdata_reg(15 downto 0);
-- Config: packet pattern sel id
regs_o.inj_ctrl_pic_conf_sel_o <= wrdata_reg(18 downto 16);
-- Interframe GAP config valid
regs_o.inj_ctrl_pic_valid_o <= wrdata_reg(20);
-- Config: packet generate mode
regs_o.inj_ctrl_pic_conf_mode_o <= wrdata_reg(22 downto 20);
-- Config: valid
regs_o.inj_ctrl_pic_conf_valid_o <= wrdata_reg(23);
-- Frame Generation Enabled
regs_o.inj_ctrl_pic_ena_o <= wrdata_reg(21);
regs_o.inj_ctrl_pic_ena_o <= wrdata_reg(24);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/wr_endpoint/ep_wishbone_controller.wb
View file @ 7f7f0255
......@@ -690,12 +690,21 @@ peripheral {
load = LOAD_EXT;
};
field {
name = "Config: packet generate mode";
prefix = "PIC_CONF_MODE";
size = 3;
type = SLV;
align= 4;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Interframe GAP config valid";
prefix = "PIC_VALID";
name = "Config: valid";
prefix = "PIC_CONF_VALID";
type = BIT;
align = 4;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
......@@ -704,6 +713,7 @@ peripheral {
name = "Frame Generation Enabled";
prefix = "PIC_ENA";
type = BIT;
align = 4;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
......
sim/endpoint_regs.v
View file @ 7f7f0255
......@@ -120,7 +120,9 @@
`define EP_INJ_CTRL_PIC_CONF_IFG 32'h0000ffff
`define EP_INJ_CTRL_PIC_CONF_SEL_OFFSET 16
`define EP_INJ_CTRL_PIC_CONF_SEL 32'h00070000
`define EP_INJ_CTRL_PIC_VALID_OFFSET 20
`define EP_INJ_CTRL_PIC_VALID 32'h00100000
`define EP_INJ_CTRL_PIC_ENA_OFFSET 21
`define EP_INJ_CTRL_PIC_ENA 32'h00200000
`define EP_INJ_CTRL_PIC_CONF_MODE_OFFSET 20
`define EP_INJ_CTRL_PIC_CONF_MODE 32'h00700000
`define EP_INJ_CTRL_PIC_CONF_VALID_OFFSET 23
`define EP_INJ_CTRL_PIC_CONF_VALID 32'h00800000
`define EP_INJ_CTRL_PIC_ENA_OFFSET 24
`define EP_INJ_CTRL_PIC_ENA 32'h01000000
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