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White Rabbit core collection
Commit 8102d8cf authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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endpoint: record-based debug for chipscope

parent 287a98b9
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Showing with 109 additions and 53 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 8102d8cf
...@@ -53,6 +53,45 @@ package endpoint_pkg is ...@@ -53,6 +53,45 @@ package endpoint_pkg is
type t_txtsu_timestamp_array is array(integer range <>) of t_txtsu_timestamp; type t_txtsu_timestamp_array is array(integer range <>) of t_txtsu_timestamp;
-- Endpoint's internal fabric used to connect the submodules with each other.
-- Easier to handle than pipelined Wishbone.
type t_ep_internal_fabric is record
sof : std_logic;
eof : std_logic;
error : std_logic;
dvalid : std_logic;
bytesel : std_logic;
has_rx_timestamp : std_logic;
rx_timestamp_valid : std_logic;
data : std_logic_vector(15 downto 0);
addr : std_logic_vector(1 downto 0);
end record;
type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;
-- debug CS types
type t_dbg_ep_rxpcs is record
fsm : std_logic_vector(2 downto 0);
end record;
type t_dbg_ep_pcs is record
rx : t_dbg_ep_rxpcs;
end record;
type t_dbg_ep_rxpath is record
fab_pipe : t_fab_pipe(9 downto 0);
dreq_pipe : std_logic_vector(9 downto 0);
pcs_fifo_afull : std_logic;
pcs_fifo_empty : std_logic;
pcs_fifo_full : std_logic;
rxbuf_full : std_logic;
end record;
type t_dbg_ep is record
pcs : t_dbg_ep_pcs;
rxpath : t_dbg_ep_rxpath;
end record;
------------------------------------
constant c_epevents_sz : integer := 29; --how many events the endpoint generates constant c_epevents_sz : integer := 29; --how many events the endpoint generates
component xwr_endpoint component xwr_endpoint
...@@ -145,9 +184,9 @@ package endpoint_pkg is ...@@ -145,9 +184,9 @@ package endpoint_pkg is
led_act_o : out std_logic; led_act_o : out std_logic;
link_kill_i : in std_logic := '0'; link_kill_i : in std_logic := '0';
link_up_o : out std_logic; link_up_o : out std_logic;
dbg_o : out std_logic_vector(63 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0)); nice_dbg_o : out t_dbg_ep);
end component; end component;
component wr_endpoint component wr_endpoint
...@@ -262,9 +301,9 @@ package endpoint_pkg is ...@@ -262,9 +301,9 @@ package endpoint_pkg is
led_act_o : out std_logic; led_act_o : out std_logic;
link_kill_i : in std_logic := '0'; link_kill_i : in std_logic := '0';
link_up_o : out std_logic; link_up_o : out std_logic;
dbg_o : out std_logic_vector(63 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0)); nice_dbg_o : out t_dbg_ep);
end component; end component;
constant c_xwr_endpoint_sdb : t_sdb_device := ( constant c_xwr_endpoint_sdb : t_sdb_device := (
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 8102d8cf
...@@ -112,20 +112,6 @@ package endpoint_private_pkg is ...@@ -112,20 +112,6 @@ package endpoint_private_pkg is
rx_drop_at_rtu_full : std_logic; rx_drop_at_rtu_full : std_logic;
end record; end record;
-- Endpoint's internal fabric used to connect the submodules with each other.
-- Easier to handle than pipelined Wishbone.
type t_ep_internal_fabric is record
sof : std_logic;
eof : std_logic;
error : std_logic;
dvalid : std_logic;
bytesel : std_logic;
has_rx_timestamp : std_logic;
rx_timestamp_valid : std_logic;
data : std_logic_vector(15 downto 0);
addr : std_logic_vector(1 downto 0);
end record;
component ep_1000basex_pcs component ep_1000basex_pcs
generic ( generic (
g_simulation : boolean); g_simulation : boolean);
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ 8102d8cf
...@@ -52,6 +52,7 @@ use ieee.numeric_std.all; ...@@ -52,6 +52,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
entity ep_1000basex_pcs is entity ep_1000basex_pcs is
...@@ -180,8 +181,8 @@ entity ep_1000basex_pcs is ...@@ -180,8 +181,8 @@ entity ep_1000basex_pcs is
mdio_ready_o : out std_logic; mdio_ready_o : out std_logic;
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0) dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
); nice_dbg_o : out t_dbg_ep_pcs);
end ep_1000basex_pcs; end ep_1000basex_pcs;
...@@ -291,7 +292,8 @@ architecture rtl of ep_1000basex_pcs is ...@@ -291,7 +292,8 @@ architecture rtl of ep_1000basex_pcs is
an_idle_match_o : out std_logic; an_idle_match_o : out std_logic;
rmon_rx_overrun : out std_logic; rmon_rx_overrun : out std_logic;
rmon_rx_inv_code : out std_logic; rmon_rx_inv_code : out std_logic;
rmon_rx_sync_lost : out std_logic); rmon_rx_sync_lost : out std_logic;
nice_dbg_o : out t_dbg_ep_rxpcs);
end component; end component;
...@@ -484,7 +486,9 @@ begin -- rtl ...@@ -484,7 +486,9 @@ begin -- rtl
phy_rx_clk_i => serdes_rx_clk_i, phy_rx_clk_i => serdes_rx_clk_i,
phy_rx_data_i => serdes_rx_data_i, phy_rx_data_i => serdes_rx_data_i,
phy_rx_k_i => serdes_rx_k_i, phy_rx_k_i => serdes_rx_k_i,
phy_rx_enc_err_i => serdes_rx_enc_err_i phy_rx_enc_err_i => serdes_rx_enc_err_i,
nice_dbg_o => nice_dbg_o.rx
); );
......
modules/wr_endpoint/ep_clock_alignment_fifo.vhd
View file @ 8102d8cf
...@@ -41,6 +41,7 @@ use ieee.numeric_std.all; ...@@ -41,6 +41,7 @@ use ieee.numeric_std.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity ep_clock_alignment_fifo is entity ep_clock_alignment_fifo is
......
modules/wr_endpoint/ep_packet_filter.vhd
View file @ 8102d8cf
...@@ -42,6 +42,7 @@ use ieee.numeric_std.all; ...@@ -42,6 +42,7 @@ use ieee.numeric_std.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
entity ep_packet_filter is entity ep_packet_filter is
......
modules/wr_endpoint/ep_rtu_header_extract.vhd
View file @ 8102d8cf
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity ep_rtu_header_extract is entity ep_rtu_header_extract is
......
modules/wr_endpoint/ep_rx_buffer.vhd
View file @ 8102d8cf
...@@ -42,6 +42,7 @@ library work; ...@@ -42,6 +42,7 @@ library work;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
......
modules/wr_endpoint/ep_rx_crc_size_check.vhd
View file @ 8102d8cf
...@@ -5,6 +5,7 @@ use ieee.numeric_std.all; ...@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.gencores_pkg.all; -- for gc_crc_gen use work.gencores_pkg.all; -- for gc_crc_gen
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
use work.ep_crc32_pkg.all; use work.ep_crc32_pkg.all;
......
modules/wr_endpoint/ep_rx_early_address_match.vhd
View file @ 8102d8cf
...@@ -5,6 +5,7 @@ use ieee.numeric_std.all; ...@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.gencores_pkg.all; -- for gc_crc_gen use work.gencores_pkg.all; -- for gc_crc_gen
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
-- 1st stage in the RX pipeline: early address matching/header parsing -- 1st stage in the RX pipeline: early address matching/header parsing
......
modules/wr_endpoint/ep_rx_oob_insert.vhd
View file @ 8102d8cf
...@@ -5,6 +5,7 @@ use ieee.numeric_std.all; ...@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.gencores_pkg.all; -- for gc_crc_gen use work.gencores_pkg.all; -- for gc_crc_gen
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
......
modules/wr_endpoint/ep_rx_path.vhd
View file @ 8102d8cf
...@@ -55,6 +55,7 @@ use ieee.numeric_std.all; ...@@ -55,6 +55,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
...@@ -106,7 +107,8 @@ entity ep_rx_path is ...@@ -106,7 +107,8 @@ entity ep_rx_path is
rtu_full_i : in std_logic; rtu_full_i : in std_logic;
rtu_rq_valid_o : out std_logic; rtu_rq_valid_o : out std_logic;
rtu_rq_abort_o : out std_logic; rtu_rq_abort_o : out std_logic;
dbg_o : out std_logic_vector(29 downto 0)
nice_dbg_o : out t_dbg_ep_rxpath
); );
end ep_rx_path; end ep_rx_path;
...@@ -304,8 +306,6 @@ architecture behavioral of ep_rx_path is ...@@ -304,8 +306,6 @@ architecture behavioral of ep_rx_path is
signal tmp_dat : std_logic_vector(15 downto 0); signal tmp_dat : std_logic_vector(15 downto 0);
type t_fab_pipe is array(integer range <>) of t_ep_internal_fabric;
signal fab_pipe : t_fab_pipe(0 to 9); signal fab_pipe : t_fab_pipe(0 to 9);
signal dreq_pipe : std_logic_vector(9 downto 0); signal dreq_pipe : std_logic_vector(9 downto 0);
...@@ -457,11 +457,12 @@ begin -- behavioral ...@@ -457,11 +457,12 @@ begin -- behavioral
dreq_i => dreq_pipe(3), dreq_i => dreq_pipe(3),
fab_i => fab_pipe(2), fab_i => fab_pipe(2),
fab_o => fab_pipe(3), fab_o => fab_pipe(3),
full_o => open, full_o => nice_dbg_o.pcs_fifo_full,
empty_o => open, empty_o => nice_dbg_o.pcs_fifo_empty,
almostfull_o => pcs_fifo_almostfull_o, almostfull_o => pcs_fifo_almostfull,
pass_threshold_i => std_logic_vector(to_unsigned(32, 7))); -- fixme: add pass_threshold_i => std_logic_vector(to_unsigned(32, 7))); -- fixme: add
-- register -- register
pcs_fifo_almostfull_o <= pcs_fifo_almostfull;
U_Insert_OOB : ep_rx_oob_insert U_Insert_OOB : ep_rx_oob_insert
port map ( port map (
...@@ -649,11 +650,12 @@ begin -- behavioral ...@@ -649,11 +650,12 @@ begin -- behavioral
rmon_o.rx_tclass(7) <= rtu_rq_valid when (vlan_tclass = "111" and vlan_is_tagged = '1') else '0'; rmon_o.rx_tclass(7) <= rtu_rq_valid when (vlan_tclass = "111" and vlan_is_tagged = '1') else '0';
GEN_DBG: for i in 0 to 9 generate GEN_DBG: for i in 0 to 9 generate
dbg_o(i) <= fab_pipe(i).sof; nice_dbg_o.fab_pipe(i) <= fab_pipe(i);
dbg_o(i+10) <= fab_pipe(i).eof; nice_dbg_o.dreq_pipe(i)<= dreq_pipe(i);
dbg_o(i+20) <= dreq_pipe(i);
end generate GEN_DBG; end generate GEN_DBG;
nice_dbg_o.pcs_fifo_afull <= pcs_fifo_almostfull;
nice_dbg_o.rxbuf_full <= rxbuf_full;
end behavioral; end behavioral;
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
View file @ 8102d8cf
...@@ -48,6 +48,7 @@ use ieee.numeric_std.all; ...@@ -48,6 +48,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity ep_rx_pcs_16bit is entity ep_rx_pcs_16bit is
generic ( generic (
...@@ -102,7 +103,9 @@ entity ep_rx_pcs_16bit is ...@@ -102,7 +103,9 @@ entity ep_rx_pcs_16bit is
-- RMON events -- RMON events
rmon_rx_overrun : out std_logic; rmon_rx_overrun : out std_logic;
rmon_rx_inv_code : out std_logic; rmon_rx_inv_code : out std_logic;
rmon_rx_sync_lost : out std_logic rmon_rx_sync_lost : out std_logic;
nice_dbg_o : out t_dbg_ep_rxpcs
); );
end ep_rx_pcs_16bit; end ep_rx_pcs_16bit;
...@@ -743,6 +746,12 @@ begin ...@@ -743,6 +746,12 @@ begin
pcs_fab_o.rx_timestamp_valid <= timestamp_valid_i; pcs_fab_o.rx_timestamp_valid <= timestamp_valid_i;
nice_dbg_o.fsm <= "000" when (rx_state = RX_NOFRAME) else
"001" when (rx_state = RX_CR) else
"010" when (rx_state = RX_SPD_PREAMBLE) else
"011" when (rx_state = RX_PAYLOAD) else
"100" when (rx_state = RX_EXTEND);
end behavioral; end behavioral;
modules/wr_endpoint/ep_rx_pcs_8bit.vhd
View file @ 8102d8cf
...@@ -53,6 +53,7 @@ library work; ...@@ -53,6 +53,7 @@ library work;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity ep_rx_pcs_8bit is entity ep_rx_pcs_8bit is
generic ( generic (
......
modules/wr_endpoint/ep_rx_status_reg_insert.vhd
View file @ 8102d8cf
...@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all; ...@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
entity ep_rx_status_reg_insert is entity ep_rx_status_reg_insert is
......
modules/wr_endpoint/ep_rx_vlan_unit.vhd
View file @ 8102d8cf
...@@ -4,6 +4,7 @@ use ieee.numeric_std.all; ...@@ -4,6 +4,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
......
modules/wr_endpoint/ep_rx_wb_master.vhd
View file @ 8102d8cf
...@@ -27,6 +27,7 @@ use ieee.numeric_std.all; ...@@ -27,6 +27,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
entity ep_rx_wb_master is entity ep_rx_wb_master is
......
modules/wr_endpoint/ep_tx_crc_inserter.vhd
View file @ 8102d8cf
...@@ -42,6 +42,7 @@ library work; ...@@ -42,6 +42,7 @@ library work;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
use work.ep_crc32_pkg.all; use work.ep_crc32_pkg.all;
......
modules/wr_endpoint/ep_tx_header_processor.vhd
View file @ 8102d8cf
...@@ -46,6 +46,7 @@ use work.gencores_pkg.all; ...@@ -46,6 +46,7 @@ use work.gencores_pkg.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
entity ep_tx_header_processor is entity ep_tx_header_processor is
......
modules/wr_endpoint/ep_tx_inject_ctrl.vhd
View file @ 8102d8cf
...@@ -42,6 +42,7 @@ use ieee.numeric_std.all; ...@@ -42,6 +42,7 @@ use ieee.numeric_std.all;
library work; library work;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
entity ep_tx_inject_ctrl is entity ep_tx_inject_ctrl is
......
modules/wr_endpoint/ep_tx_packet_injection.vhd
View file @ 8102d8cf
...@@ -50,6 +50,7 @@ use ieee.std_logic_1164.all; ...@@ -50,6 +50,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity ep_tx_packet_injection is entity ep_tx_packet_injection is
......
modules/wr_endpoint/ep_tx_path.vhd
View file @ 8102d8cf
...@@ -42,6 +42,7 @@ use ieee.std_logic_1164.all; ...@@ -42,6 +42,7 @@ use ieee.std_logic_1164.all;
library work; library work;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
entity ep_tx_path is entity ep_tx_path is
...@@ -136,7 +137,6 @@ entity ep_tx_path is ...@@ -136,7 +137,6 @@ entity ep_tx_path is
ep_ctrl_i : in std_logic :='1'; ep_ctrl_i : in std_logic :='1';
regs_i : in t_ep_out_registers; regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers; regs_o : out t_ep_in_registers;
-- dbg_o : out std_logic_vector(11 downto 0)
dbg_o : out std_logic_vector(33 downto 0) dbg_o : out std_logic_vector(33 downto 0)
); );
......
modules/wr_endpoint/ep_tx_pcs_16bit.vhd
View file @ 8102d8cf
...@@ -53,6 +53,7 @@ library work; ...@@ -53,6 +53,7 @@ library work;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity ep_tx_pcs_16bit is entity ep_tx_pcs_16bit is
......
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
View file @ 8102d8cf
...@@ -60,6 +60,7 @@ library work; ...@@ -60,6 +60,7 @@ library work;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity ep_tx_pcs_8bit is entity ep_tx_pcs_8bit is
......
modules/wr_endpoint/ep_tx_vlan_unit.vhd
View file @ 8102d8cf
...@@ -55,6 +55,7 @@ use work.gencores_pkg.all; ...@@ -55,6 +55,7 @@ use work.gencores_pkg.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
use work.endpoint_private_pkg.all; use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all; use work.ep_wbgen2_pkg.all;
entity ep_tx_vlan_unit is entity ep_tx_vlan_unit is
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 8102d8cf
...@@ -286,9 +286,10 @@ entity wr_endpoint is ...@@ -286,9 +286,10 @@ entity wr_endpoint is
-- HI indicates that link is up (so cable connected), LOW indicates that link is faulty -- HI indicates that link is up (so cable connected), LOW indicates that link is faulty
-- (e.g.: cable disconnected) -- (e.g.: cable disconnected)
link_up_o : out std_logic; link_up_o : out std_logic;
dbg_o : out std_logic_vector(63 downto 0);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0) dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep
); );
end wr_endpoint; end wr_endpoint;
...@@ -399,7 +400,7 @@ architecture syn of wr_endpoint is ...@@ -399,7 +400,7 @@ architecture syn of wr_endpoint is
rtu_full_i : in std_logic; rtu_full_i : in std_logic;
rtu_rq_valid_o : out std_logic; rtu_rq_valid_o : out std_logic;
rtu_rq_abort_o : out std_logic; rtu_rq_abort_o : out std_logic;
dbg_o : out std_logic_vector(29 downto 0)); nice_dbg_o : out t_dbg_ep_rxpath);
end component; end component;
component ep_1000basex_pcs component ep_1000basex_pcs
...@@ -444,8 +445,9 @@ architecture syn of wr_endpoint is ...@@ -444,8 +445,9 @@ architecture syn of wr_endpoint is
mdio_stb_i : in std_logic; mdio_stb_i : in std_logic;
mdio_rw_i : in std_logic; mdio_rw_i : in std_logic;
mdio_ready_o : out std_logic; mdio_ready_o : out std_logic;
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0)); dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep_pcs);
end component; end component;
component ep_timestamping_unit component ep_timestamping_unit
...@@ -704,7 +706,8 @@ begin ...@@ -704,7 +706,8 @@ begin
mdio_rw_i => regs_fromwb.mdio_cr_rw_o, mdio_rw_i => regs_fromwb.mdio_cr_rw_o,
mdio_ready_o => regs_towb_ep.mdio_asr_ready_i, mdio_ready_o => regs_towb_ep.mdio_asr_ready_i,
dbg_tx_pcs_wr_count_o => dbg_tx_pcs_wr_count_o, dbg_tx_pcs_wr_count_o => dbg_tx_pcs_wr_count_o,
dbg_tx_pcs_rd_count_o => dbg_tx_pcs_rd_count_o ); dbg_tx_pcs_rd_count_o => dbg_tx_pcs_rd_count_o,
nice_dbg_o => nice_dbg_o.pcs);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -753,10 +756,7 @@ begin ...@@ -753,10 +756,7 @@ begin
inject_req_i => inject_req_i, inject_req_i => inject_req_i,
inject_user_value_i => inject_user_value_i, inject_user_value_i => inject_user_value_i,
inject_packet_sel_i => inject_packet_sel_i, inject_packet_sel_i => inject_packet_sel_i,
inject_ready_o => inject_ready_o, inject_ready_o => inject_ready_o);
dbg_o => dbg_o(63 downto 30)
-- dbg_o => dbg_o(43 downto 32)
);
txfra_flow_enable <= '1'; txfra_flow_enable <= '1';
...@@ -816,8 +816,7 @@ begin ...@@ -816,8 +816,7 @@ begin
rtu_rq_abort_o => rtu_rq_abort_o, rtu_rq_abort_o => rtu_rq_abort_o,
src_wb_o => src_out, src_wb_o => src_out,
src_wb_i => src_in, src_wb_i => src_in,
dbg_o => dbg_o(29 downto 0) nice_dbg_o => nice_dbg_o.rxpath);
);
rtu_rq_smac_o <= rtu_rq.smac; rtu_rq_smac_o <= rtu_rq.smac;
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 8102d8cf
...@@ -248,10 +248,9 @@ entity xwr_endpoint is ...@@ -248,10 +248,9 @@ entity xwr_endpoint is
link_kill_i : in std_logic := '0'; link_kill_i : in std_logic := '0';
link_up_o : out std_logic; link_up_o : out std_logic;
dbg_o : out std_logic_vector(63 downto 0);
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0); dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0) dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
); nice_dbg_o : out t_dbg_ep);
end xwr_endpoint; end xwr_endpoint;
...@@ -371,9 +370,9 @@ begin ...@@ -371,9 +370,9 @@ begin
inject_user_value_i => inject_user_value_i, inject_user_value_i => inject_user_value_i,
inject_packet_sel_i => inject_packet_sel_i, inject_packet_sel_i => inject_packet_sel_i,
inject_ready_o => inject_ready_o, inject_ready_o => inject_ready_o,
dbg_o => dbg_o,
dbg_tx_pcs_wr_count_o=>dbg_tx_pcs_wr_count_o, dbg_tx_pcs_wr_count_o=>dbg_tx_pcs_wr_count_o,
dbg_tx_pcs_rd_count_o=>dbg_tx_pcs_rd_count_o); dbg_tx_pcs_rd_count_o=>dbg_tx_pcs_rd_count_o,
nice_dbg_o => nice_dbg_o);
wb_o.err <= '0'; wb_o.err <= '0';
wb_o.rty <= '0'; wb_o.rty <= '0';
......
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