Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
8299d657
Commit
8299d657
authored
Apr 03, 2020
by
Grzegorz Daniluk
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
lpdc: allow WRS shutting down the interface without breaking Tx LPDC
parent
4e39ff0f
Pipeline
#239
failed with stages
in 1 minute and 25 seconds
Changes
1
Pipelines
3
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
22 additions
and
10 deletions
+22
-10
wr_gtx_phy_virtex6_lp.vhd
...gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
+22
-10
No files found.
platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
View file @
8299d657
...
...
@@ -111,7 +111,8 @@ entity wr_gtx_phy_virtex6_lp is
rx_bitslide_o
:
out
std_logic_vector
(
4
downto
0
);
-- reset input, active hi
rst_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
rx_pdown_i
:
in
std_logic
:
=
'0'
;
loopen_i
:
in
std_logic
;
pad_txn_o
:
out
std_logic
;
...
...
@@ -284,7 +285,8 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
return
rv
;
end
f_reverse_bits
;
signal
gtx_rst_n
:
std_logic
;
signal
rx_rst
,
rx_rst_n
:
std_logic
;
signal
rx_pdown_d0
,
rx_pdown_synced
:
std_logic
;
signal
dbg_rst
:
std_logic
;
signal
dbg_shift_en
,
dbg_shift_en_p
:
std_logic
;
...
...
@@ -303,7 +305,7 @@ begin -- rtl
tx_sw_reset
<=
lpc_ctrl_i
(
0
);
tx_enable
<=
lpc_ctrl_i
(
1
);
rx_enable
<=
lpc_ctrl_i
(
2
);
rx_sw_reset
<=
lpc_ctrl_i
(
3
);
rx_sw_reset
<=
lpc_ctrl_i
(
3
)
or
rx_rst
;
rx_cdr_reset_a
<=
lpc_ctrl_i
(
4
);
pll_tx_reset_a
<=
lpc_ctrl_i
(
5
);
pll_rx_reset_a
<=
lpc_ctrl_i
(
6
);
...
...
@@ -313,7 +315,7 @@ begin -- rtl
dbg_data
<=
dbg_reg
(
0
);
cd_reset
<=
gt
x_rst
or
lpc_ctrl_i
(
11
);
cd_reset
<=
r
x_rst
or
lpc_ctrl_i
(
11
);
U_SyncDBG
:
gc_sync_ffs
port
map
(
...
...
@@ -417,6 +419,18 @@ begin -- rtl
gtx_rst
<=
rst_synced
or
std_logic
(
not
reset_counter
(
reset_counter
'left
));
p_gen_rx_pdown
:
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
rx_pdown_d0
<=
rx_pdown_i
;
rx_pdown_synced
<=
rx_pdown_d0
;
end
if
;
end
process
;
rx_rst
<=
gtx_rst
or
rx_pdown_synced
;
rx_rst_n
<=
not
rx_rst
;
U_Tx_Reset_Gen
:
entity
work
.
gtx_tx_reset_lp
port
map
(
...
...
@@ -564,12 +578,10 @@ begin -- rtl
end
if
;
end
process
;
gtx_rst_n
<=
not
gtx_rst
;
U_Dec1
:
gc_dec_8b10b
port
map
(
clk_i
=>
rx_rec_clk
,
rst_n_i
=>
gt
x_rst_n
,
rst_n_i
=>
r
x_rst_n
,
in_10b_i
=>
(
rx_data_raw
(
19
downto
10
)),
ctrl_o
=>
rx_k_int
(
1
),
code_err_o
=>
rx_code_err
(
1
),
...
...
@@ -579,7 +591,7 @@ begin -- rtl
U_Dec2
:
gc_dec_8b10b
port
map
(
clk_i
=>
rx_rec_clk
,
rst_n_i
=>
gt
x_rst_n
,
rst_n_i
=>
r
x_rst_n
,
in_10b_i
=>
(
rx_data_raw
(
9
downto
0
)),
ctrl_o
=>
rx_k_int
(
0
),
code_err_o
=>
rx_code_err
(
0
),
...
...
@@ -591,9 +603,9 @@ begin -- rtl
lpc_stat_o
(
1
)
<=
link_up
;
lpc_stat_o
(
2
)
<=
link_aligned
;
p_gen_rx_outputs
:
process
(
rx_rec_clk
,
gt
x_rst
)
p_gen_rx_outputs
:
process
(
rx_rec_clk
,
r
x_rst
)
begin
if
(
gt
x_rst
=
'1'
)
then
if
(
r
x_rst
=
'1'
)
then
rx_data_o_int
<=
(
others
=>
'0'
);
rx_k_o_int
<=
(
others
=>
'0'
);
rx_enc_err_o_int
<=
'0'
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment