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White Rabbit core collection
Commit 836bec09 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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xwrc_board_[common|spec] connect all this fractional-N softpll stuff through the… 

xwrc_board_[common|spec] connect all this fractional-N softpll stuff through the numerous layers of wrappers... :/
parent 6fea7129
Pipeline #4403 failed with stage
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    board/common/xwrc_board_common.vhd
    View file @ 836bec09
    ......@@ -45,6 +45,7 @@ use work.wr_fabric_pkg.all;
    use work.endpoint_pkg.all;
    use work.streamers_pkg.all;
    use work.wr_board_pkg.all;
    use work.softpll_pkg.all;
    entity xwrc_board_common is
    generic(
    ......@@ -80,6 +81,7 @@ entity xwrc_board_common is
    -- if WRPC supports only one SFP but we have two connected that are muxed,
    -- mux also the I2C acess to their memory
    g_sfp_i2c_mux_enable : boolean := FALSE;
    g_softpll_aux_channel_config : t_softpll_channels_config_array := c_softpll_default_channels_config;
    g_fabric_iface : t_board_fabric_iface := PLAIN);
    port(
    ---------------------------------------------------------------------------
    ......@@ -90,7 +92,7 @@ entity xwrc_board_common is
    -- DDMTD offset clock (125.x MHz)
    clk_dmtd_i : in std_logic;
    clk_dmtd_over_i : in std_logic := '0';
    -- Timing reference (125 MHz)
    clk_ref_i : in std_logic;
    ......@@ -266,7 +268,10 @@ entity xwrc_board_common is
    pps_p_o : out std_logic;
    pps_led_o : out std_logic;
    -- Link ok indication
    link_ok_o : out std_logic
    link_ok_o : out std_logic;
    spll_debug_o : out std_logic_vector(5 downto 0)
    );
    end entity xwrc_board_common;
    ......@@ -370,7 +375,7 @@ begin -- architecture struct
    -- The WR PTP core itself
    -----------------------------------------------------------------------------
    cmp_xwr_core : xwr_core
    cmp_xwr_core : entity work.xwr_core
    generic map (
    g_simulation => g_simulation,
    g_verbose => g_verbose,
    ......@@ -398,10 +403,12 @@ begin -- architecture struct
    g_diag_ver => c_diag_ver,
    g_diag_ro_size => c_diag_ro_size,
    g_diag_rw_size => c_diag_rw_size,
    g_dac_bits => g_dac_bits)
    g_dac_bits => g_dac_bits,
    g_softpll_aux_channel_config => g_softpll_aux_channel_config)
    port map (
    clk_sys_i => clk_sys_i,
    clk_dmtd_i => clk_dmtd_i,
    clk_dmtd_over_i => clk_dmtd_over_i,
    clk_ref_i => clk_ref_i,
    clk_aux_i => clk_aux_i,
    clk_ext_i => clk_10m_ext_i,
    ......@@ -489,7 +496,8 @@ begin -- architecture struct
    rst_aux_n_o => aux_rst_n,
    aux_diag_i => aux_diag_in,
    aux_diag_o => aux_diag_out,
    link_ok_o => link_ok);
    link_ok_o => link_ok,
    spll_debug_o => spll_debug_o);
    pps_csync_o <= pps_csync;
    pps_valid_o <= pps_valid;
    ......
    board/spec/xwrc_board_spec.vhd
    View file @ 836bec09
    ......@@ -49,6 +49,7 @@ use work.streamers_pkg.all;
    use work.wr_xilinx_pkg.all;
    use work.wr_board_pkg.all;
    use work.wr_spec_pkg.all;
    use work.softpll_pkg.all;
    library unisim;
    use unisim.vcomponents.all;
    ......@@ -81,8 +82,8 @@ entity xwrc_board_spec is
    g_diag_rw_size : integer := 0;
    -- User-defined PLL_BASE outputs config
    g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT;
    g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
    );
    g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
    g_softpll_aux_channel_config : t_softpll_channels_config_array := c_softpll_default_channels_config);
    port (
    ---------------------------------------------------------------------------
    -- Clocks/resets
    ......@@ -263,7 +264,8 @@ entity xwrc_board_spec is
    pps_valid_o : out std_logic;
    pps_led_o : out std_logic;
    -- Link ok indication
    link_ok_o : out std_logic
    link_ok_o : out std_logic;
    spll_debug_o : out std_logic_vector(5 downto 0)
    );
    end entity xwrc_board_spec;
    ......@@ -282,6 +284,7 @@ architecture struct of xwrc_board_spec is
    signal clk_pll_62m5 : std_logic;
    signal clk_pll_125m : std_logic;
    signal clk_pll_dmtd : std_logic;
    signal clk_pll_dmtd_over : std_logic;
    signal pll_locked : std_logic;
    signal clk_10m_ext : std_logic;
    signal clk_pll_aux : std_logic_vector(3 downto 0);
    ......@@ -329,7 +332,7 @@ begin -- architecture struct
    I => clk_125m_pllref_p_i,
    IB => clk_125m_pllref_n_i);
    cmp_xwrc_platform : xwrc_platform_xilinx
    cmp_xwrc_platform : entity work.xwrc_platform_xilinx
    generic map (
    g_fpga_family => "spartan6",
    g_with_external_clock_input => g_with_external_clock_input,
    ......@@ -355,6 +358,7 @@ begin -- architecture struct
    clk_62m5_sys_o => clk_pll_62m5,
    clk_125m_ref_o => clk_pll_125m,
    clk_62m5_dmtd_o => clk_pll_dmtd,
    clk_250m_dmtd_over_o => clk_pll_dmtd_over,
    pll_locked_o => pll_locked,
    clk_10m_ext_o => clk_10m_ext,
    phy8_o => phy8_to_wrc,
    ......@@ -432,7 +436,7 @@ begin -- architecture struct
    -- The WR PTP core with optional fabric interface attached
    -----------------------------------------------------------------------------
    cmp_board_common : xwrc_board_common
    cmp_board_common : entity work.xwrc_board_common
    generic map (
    g_simulation => g_simulation,
    g_verbose => g_verbose,
    ......@@ -451,7 +455,7 @@ begin -- architecture struct
    g_interface_mode => PIPELINED,
    g_address_granularity => BYTE,
    g_aux_sdb => g_aux_sdb,
    g_softpll_enable_debugger => FALSE,
    g_softpll_enable_debugger => TRUE,
    g_vuart_fifo_size => 1024,
    g_pcs_16bit => FALSE,
    g_diag_id => g_diag_id,
    ......@@ -461,11 +465,13 @@ begin -- architecture struct
    g_streamers_op_mode => g_streamers_op_mode,
    g_tx_streamer_params => g_tx_streamer_params,
    g_rx_streamer_params => g_rx_streamer_params,
    g_fabric_iface => g_fabric_iface
    g_fabric_iface => g_fabric_iface,
    g_softpll_aux_channel_config => g_softpll_aux_channel_config
    )
    port map (
    clk_sys_i => clk_pll_62m5,
    clk_dmtd_i => clk_pll_dmtd,
    clk_dmtd_over_i => clk_pll_dmtd_over,
    clk_ref_i => clk_pll_125m,
    clk_aux_i => clk_aux_i,
    clk_10m_ext_i => clk_10m_ext,
    ......@@ -546,7 +552,8 @@ begin -- architecture struct
    pps_csync_o => pps_csync_o,
    pps_valid_o => pps_valid_o,
    pps_led_o => pps_led_o,
    link_ok_o => link_ok_o);
    link_ok_o => link_ok_o,
    spll_debug_o => spll_debug_o);
    sfp_rate_select_o <= '1';
    ......
    modules/wr_softpll_ng/wr_softpll_ng.vhd
    View file @ 836bec09
    ......@@ -6,7 +6,7 @@
    -- Author : Tomasz Włostowski
    -- Company : CERN BE-CO-HT
    -- Created : 2011-01-29
    -- Last update: 2022-01-28
    -- Last update: 2023-04-03
    -- Platform : FPGA-generic
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    ......@@ -113,14 +113,14 @@ entity wr_softpll_ng is
    -- DMTD Offset clock
    clk_dmtd_i : in std_logic;
    clk_dmtd_over_i : in std_logic;
    clk_dmtd_over_i : in std_logic := '0';
    -- External reference clock (e.g. 10 MHz from Cesium/GPSDO). Used only if
    -- g_num_exts > 0
    clk_ext_i : in std_logic;
    clk_ext_i : in std_logic := '0';
    -- External clock, multiplied to 125 MHz using the FPGA's PLL
    clk_ext_mul_i : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0);
    clk_ext_mul_i : in std_logic_vector(f_nonzero_vector(g_num_exts)-1 downto 0) := (others => '0');
    clk_ext_mul_locked_i : in std_logic := '1';
    clk_ext_stopped_i : in std_logic := '0';
    clk_ext_rst_o : out std_logic;
    ......@@ -451,7 +451,7 @@ begin -- rtl
    end generate gen_feedback_dmtds;
    -- drive unused debug output
    debug_o(4) <= '0';
    -- debug_o(4) <= '0';
    gen_ext_dmtds: for I in 0 to g_num_exts-1 generate
    ......@@ -487,9 +487,9 @@ begin -- rtl
    end generate gen_ext_dmtds;
    gen_with_ext_clock_input: if g_num_exts > 0 generate
    debug_o(0) <= fb_resync_out(0);
    debug_o(1) <= tags_p(g_num_ref_inputs + g_num_outputs);
    debug_o(2) <= tags_p(g_num_ref_inputs);
    -- debug_o(0) <= fb_resync_out(0);
    -- debug_o(1) <= tags_p(g_num_ref_inputs + g_num_outputs);
    -- debug_o(2) <= tags_p(g_num_ref_inputs);
    U_Aligner_EXT : spll_aligner
    generic map (
    ......@@ -534,11 +534,11 @@ begin -- rtl
    regs_out.eccr_ext_ref_stopped_i <= '0';
    clk_ext_rst_o <= '0';
    -- drive unused debug outputs
    debug_o(0) <= '0';
    debug_o(1) <= '0';
    debug_o(2) <= '0';
    debug_o(3) <= '0';
    debug_o(5) <= '0';
    -- debug_o(0) <= '0';
    -- debug_o(1) <= '0';
    -- debug_o(2) <= '0';
    -- debug_o(3) <= '0';
    -- debug_o(5) <= '0';
    end generate gen_without_ext_clock_input;
    p_ack_aligner_samples: process(regs_in, aligner_sample_valid)
    ......
    platform/xilinx/xwrc_platform_xilinx.vhd
    View file @ 836bec09
    ......@@ -159,6 +159,7 @@ entity xwrc_platform_xilinx is
    clk_20m_o : out std_logic;
    clk_ref_locked_o : out std_logic;
    clk_62m5_dmtd_o : out std_logic;
    clk_250m_dmtd_over_o : out std_logic;
    pll_locked_o : out std_logic;
    clk_10m_ext_o : out std_logic;
    -- PHY - CH0
    ......@@ -251,6 +252,7 @@ begin -- architecture rtl
    signal clk_sys_fb : std_logic;
    signal pll_sys_locked : std_logic;
    signal clk_dmtd : std_logic;
    signal clk_dmtd_over : std_logic;
    signal clk_dmtd_fb : std_logic;
    signal pll_dmtd_locked : std_logic;
    signal clk_20m_vcxo_buf : std_logic;
    ......@@ -364,11 +366,15 @@ begin -- architecture rtl
    CLKOUT0_DIVIDE => 16,
    CLKOUT0_PHASE => 0.000,
    CLKOUT0_DUTY_CYCLE => 0.500,
    CLKOUT1_DIVIDE => 4,
    CLKOUT1_PHASE => 0.000,
    CLKOUT1_DUTY_CYCLE => 0.500,
    CLKIN_PERIOD => 50.0,
    REF_JITTER => 0.016)
    port map (
    CLKFBOUT => clk_dmtd_fb,
    CLKOUT0 => clk_dmtd,
    CLKOUT1 => clk_dmtd_over,
    LOCKED => pll_dmtd_locked,
    RST => pll_arst,
    CLKFBIN => clk_dmtd_fb,
    ......@@ -386,6 +392,12 @@ begin -- architecture rtl
    O => clk_62m5_dmtd_o,
    I => clk_dmtd);
    -- DMTD PLL output clock buffer
    cmp_clk_dmtd_buf_over_o : BUFG
    port map (
    O => clk_250m_dmtd_over_o,
    I => clk_dmtd_over);
    gen_spartan6_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
    ......
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