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White Rabbit core collection
Commit 85ba1e88 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_softpll_ng/spll_wb_slave: added EXT_REF_PRESENT flag

parent cd48858f
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Showing with 24 additions and 5 deletions
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ 85ba1e88
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Apr 12 14:15:28 2012
-- Created : Mon Apr 16 16:49:35 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -188,7 +188,7 @@ begin
rddata_reg(1) <= regs_i.eccr_ext_supported_i;
rddata_reg(2) <= spll_eccr_align_en_int;
rddata_reg(3) <= regs_i.eccr_align_done_i;
rddata_reg(4) <= 'X';
rddata_reg(4) <= regs_i.eccr_ext_ref_present_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -795,6 +795,7 @@ begin
-- Enable PPS/phase alignment
regs_o.eccr_align_en_o <= spll_eccr_align_en_int;
-- PPS/phase alignment done
-- External Clock Reference Present
-- DMTD Clock Undersampling Divider
regs_o.dccr_gate_div_o <= spll_dccr_gate_div_int;
-- Reference Channel Undersampling Enable
......
modules/wr_softpll_ng/spll_wb_slave.wb
View file @ 85ba1e88
......@@ -97,6 +97,17 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
0: reference input dead";
prefix = "EXT_REF_PRESENT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ 85ba1e88
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Apr 12 14:15:28 2012
-- Created : Mon Apr 16 16:49:35 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -25,6 +25,7 @@ package spll_wbgen2_pkg is
csr_n_out_i : std_logic_vector(2 downto 0);
eccr_ext_supported_i : std_logic;
eccr_align_done_i : std_logic;
eccr_ext_ref_present_i : std_logic;
occr_out_en_i : std_logic_vector(7 downto 0);
rcer_i : std_logic_vector(31 downto 0);
ocer_i : std_logic_vector(7 downto 0);
......@@ -44,6 +45,7 @@ package spll_wbgen2_pkg is
csr_n_out_i => (others => '0'),
eccr_ext_supported_i => '0',
eccr_align_done_i => '0',
eccr_ext_ref_present_i => '0',
occr_out_en_i => (others => '0'),
rcer_i => (others => '0'),
ocer_i => (others => '0'),
......@@ -154,6 +156,7 @@ tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_
tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i);
tmp.eccr_ext_supported_i := f_x_to_zero(left.eccr_ext_supported_i) or f_x_to_zero(right.eccr_ext_supported_i);
tmp.eccr_align_done_i := f_x_to_zero(left.eccr_align_done_i) or f_x_to_zero(right.eccr_align_done_i);
tmp.eccr_ext_ref_present_i := f_x_to_zero(left.eccr_ext_ref_present_i) or f_x_to_zero(right.eccr_ext_ref_present_i);
tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i);
tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i);
tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i);
......
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ 85ba1e88
......@@ -188,7 +188,8 @@ architecture rtl of wr_softpll_ng is
sync_done_o : out std_logic;
err_wrap_o : out std_logic;
err_o : out std_logic_vector(g_error_bits-1 downto 0);
err_stb_o : out std_logic);
err_stb_o : out std_logic;
ref_present_o : out std_logic);
end component;
component dmtd_with_deglitcher
......@@ -373,6 +374,7 @@ architecture rtl of wr_softpll_ng is
signal dmtd_fb_clk_in, dmtd_fb_clk_dmtd : std_logic_vector(g_num_outputs-1 downto 0);
signal bb_sync_en, bb_sync_done : std_logic;
signal ext_ref_present : std_logic;
begin -- rtl
......@@ -582,12 +584,14 @@ begin -- rtl
sync_done_o => bb_sync_done,
err_o => bb_phase_err,
err_wrap_o => bb_phase_err_wrap,
err_stb_o => bb_phase_err_stb_p);
err_stb_o => bb_phase_err_stb_p,
ref_present_o => ext_ref_present);
tags(g_num_ref_inputs + g_num_outputs)(c_BB_ERROR_BITS-1 downto 0) <= bb_phase_err(c_BB_ERROR_BITS-1 downto 0);
tags(g_num_ref_inputs + g_num_outputs)(c_BB_ERROR_BITS) <= bb_phase_err_wrap;
regs_out.eccr_ext_supported_i <= '1';
regs_out.eccr_ext_ref_present_i <= ext_ref_present;
end generate gen_bb_detector;
......
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