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White Rabbit core collection
Commit 8898da15 authored by Miguel Jimenez Lopez's avatar Miguel Jimenez Lopez Committed by Grzegorz Daniluk
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spec: Changes for the SPEC board block. 

- Add generic parameter for the SDB info of the auxiliary interface of the WRPC.
- Export pps_csync and pps_valid ports from the WRPC.
parent 96903510
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Inline Side-by-side
Showing with 30 additions and 10 deletions
board/spec/wr_spec_pkg.vhd
View file @ 8898da15
...@@ -61,7 +61,9 @@ package wr_spec_pkg is ...@@ -61,7 +61,9 @@ package wr_spec_pkg is
g_diag_ver : integer := 0; g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0; g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0; g_diag_rw_size : integer := 0;
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT); g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
);
port ( port (
areset_n_i : in std_logic; areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1'; areset_edge_n_i : in std_logic := '1';
...@@ -152,6 +154,8 @@ package wr_spec_pkg is ...@@ -152,6 +154,8 @@ package wr_spec_pkg is
btn1_i : in std_logic := '1'; btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1'; btn2_i : in std_logic := '1';
pps_p_o : out std_logic; pps_p_o : out std_logic;
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_led_o : out std_logic; pps_led_o : out std_logic;
link_ok_o : out std_logic); link_ok_o : out std_logic);
end component xwrc_board_spec; end component xwrc_board_spec;
...@@ -171,7 +175,9 @@ package wr_spec_pkg is ...@@ -171,7 +175,9 @@ package wr_spec_pkg is
g_diag_id : integer := 0; g_diag_id : integer := 0;
g_diag_ver : integer := 0; g_diag_ver : integer := 0;
g_diag_ro_vector_width : integer := 0; g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0); g_diag_rw_vector_width : integer := 0;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
);
port ( port (
areset_n_i : in std_logic; areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1'; areset_edge_n_i : in std_logic := '1';
...@@ -311,6 +317,8 @@ package wr_spec_pkg is ...@@ -311,6 +317,8 @@ package wr_spec_pkg is
btn1_i : in std_logic := '1'; btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1'; btn2_i : in std_logic := '1';
pps_p_o : out std_logic; pps_p_o : out std_logic;
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_led_o : out std_logic; pps_led_o : out std_logic;
link_ok_o : out std_logic); link_ok_o : out std_logic);
end component wrc_board_spec; end component wrc_board_spec;
......
board/spec/wrc_board_spec.vhd
View file @ 8898da15
...@@ -78,7 +78,8 @@ entity wrc_board_spec is ...@@ -78,7 +78,8 @@ entity wrc_board_spec is
g_diag_ver : integer := 0; g_diag_ver : integer := 0;
-- size the generic diag interface -- size the generic diag interface
g_diag_ro_vector_width : integer := 0; g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0 g_diag_rw_vector_width : integer := 0;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
); );
port ( port (
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -302,6 +303,8 @@ entity wrc_board_spec is ...@@ -302,6 +303,8 @@ entity wrc_board_spec is
btn2_i : in std_logic := '1'; btn2_i : in std_logic := '1';
-- 1PPS output -- 1PPS output
pps_p_o : out std_logic; pps_p_o : out std_logic;
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_led_o : out std_logic; pps_led_o : out std_logic;
-- Link ok indication -- Link ok indication
link_ok_o : out std_logic link_ok_o : out std_logic
...@@ -415,10 +418,11 @@ begin -- architecture struct ...@@ -415,10 +418,11 @@ begin -- architecture struct
aux_diag_in <= f_de_vectorize_diag(aux_diag_i, g_diag_ro_vector_width); aux_diag_in <= f_de_vectorize_diag(aux_diag_i, g_diag_ro_vector_width);
aux_diag_o <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width); aux_diag_o <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width);
tstamps_stb_o <= timestamps_out.stb; tstamps_stb_o <= timestamps_out.stb;
tstamps_tsval_o <= timestamps_out.tsval; tstamps_tsval_o <= timestamps_out.tsval;
tstamps_port_id_o <= timestamps_out.port_id; tstamps_port_id_o <= timestamps_out.port_id;
tstamps_frame_id_o <= timestamps_out.frame_id; tstamps_frame_id_o <= timestamps_out.frame_id;
tstamps_incorrect_o <= timestamps_out.incorrect;
wrs_tx_cfg_in.mac_local <= wrs_tx_cfg_mac_l_i; wrs_tx_cfg_in.mac_local <= wrs_tx_cfg_mac_l_i;
wrs_tx_cfg_in.mac_target <= wrs_tx_cfg_mac_t_i; wrs_tx_cfg_in.mac_target <= wrs_tx_cfg_mac_t_i;
...@@ -446,7 +450,8 @@ begin -- architecture struct ...@@ -446,7 +450,8 @@ begin -- architecture struct
g_diag_id => g_diag_id, g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver, g_diag_ver => g_diag_ver,
g_diag_ro_size => c_diag_ro_size, g_diag_ro_size => c_diag_ro_size,
g_diag_rw_size => c_diag_rw_size) g_diag_rw_size => c_diag_rw_size,
g_aux_sdb => g_aux_sdb)
port map ( port map (
areset_n_i => areset_n_i, areset_n_i => areset_n_i,
areset_edge_n_i => areset_edge_n_i, areset_edge_n_i => areset_edge_n_i,
...@@ -534,6 +539,8 @@ begin -- architecture struct ...@@ -534,6 +539,8 @@ begin -- architecture struct
btn1_i => btn1_i, btn1_i => btn1_i,
btn2_i => btn2_i, btn2_i => btn2_i,
pps_p_o => pps_p_o, pps_p_o => pps_p_o,
pps_csync_o => pps_csync_o,
pps_valid_o => pps_valid_o,
pps_led_o => pps_led_o, pps_led_o => pps_led_o,
link_ok_o => link_ok_o); link_ok_o => link_ok_o);
......
board/spec/xwrc_board_spec.vhd
View file @ 8898da15
...@@ -80,7 +80,8 @@ entity xwrc_board_spec is ...@@ -80,7 +80,8 @@ entity xwrc_board_spec is
g_diag_ro_size : integer := 0; g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0; g_diag_rw_size : integer := 0;
-- User-defined PLL_BASE outputs config -- User-defined PLL_BASE outputs config
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
); );
port ( port (
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -256,6 +257,8 @@ entity xwrc_board_spec is ...@@ -256,6 +257,8 @@ entity xwrc_board_spec is
btn2_i : in std_logic := '1'; btn2_i : in std_logic := '1';
-- 1PPS output -- 1PPS output
pps_p_o : out std_logic; pps_p_o : out std_logic;
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_led_o : out std_logic; pps_led_o : out std_logic;
-- Link ok indication -- Link ok indication
link_ok_o : out std_logic link_ok_o : out std_logic
...@@ -444,7 +447,7 @@ begin -- architecture struct ...@@ -444,7 +447,7 @@ begin -- architecture struct
g_dpram_size => 131072/4, g_dpram_size => 131072/4,
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_aux_sdb => c_wrc_periph3_sdb, g_aux_sdb => g_aux_sdb,
g_softpll_enable_debugger => FALSE, g_softpll_enable_debugger => FALSE,
g_vuart_fifo_size => 1024, g_vuart_fifo_size => 1024,
g_pcs_16bit => FALSE, g_pcs_16bit => FALSE,
...@@ -537,6 +540,8 @@ begin -- architecture struct ...@@ -537,6 +540,8 @@ begin -- architecture struct
btn1_i => btn1_i, btn1_i => btn1_i,
btn2_i => btn2_i, btn2_i => btn2_i,
pps_p_o => pps_p_o, pps_p_o => pps_p_o,
pps_csync_o => pps_csync_o,
pps_valid_o => pps_valid_o,
pps_led_o => pps_led_o, pps_led_o => pps_led_o,
link_ok_o => link_ok_o); link_ok_o => link_ok_o);
......
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