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White Rabbit core collection
Commit 88dcf0ea authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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eca: now that the generic_dpram has the features we need, use it instead.

parent 8c372767
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Showing with 54 additions and 43 deletions
modules/wr_eca/eca_channel.vhd
View file @ 88dcf0ea
......@@ -203,6 +203,7 @@ architecture rtl of eca_channel is
signal scan_next : t_table_lo_index;
signal scan_time_p4 : t_queue_index;
signal scan_time_m4 : t_queue_index;
signal scan_valid3 : std_logic_vector(c_scanners-1 downto 0);
signal scan_valid2 : std_logic_vector(c_scanners-1 downto 0);
signal scan_valid1 : std_logic_vector(c_scanners-1 downto 0);
signal scan_lesseq : std_logic_vector(c_scanners-1 downto 0);
......@@ -264,8 +265,9 @@ begin
TSx : for table_hi_idx in 0 to c_scanners-1 generate
TS : eca_sdp
generic map(
g_addr_bits => c_table_lo_index_bits,
g_data_bits => c_time_bits+1)
g_addr_bits => c_table_lo_index_bits,
g_data_bits => c_time_bits+1,
g_dual_clock => false)
port map(
w_clk_i => clk_i,
w_en_i => ts_manage_write(table_hi_idx),
......@@ -281,8 +283,9 @@ begin
-- The data part of the table
TD : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => cd_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => cd_data_bits,
g_dual_clock => false)
port map(
w_clk_i => clk_i,
w_en_i => td_manage_write,
......@@ -303,8 +306,9 @@ begin
-- The free queue
F : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_index_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_index_bits,
g_dual_clock => false)
port map(
w_clk_i => clk_i,
w_en_i => fw_manage_free,
......@@ -411,7 +415,11 @@ begin
begin
if rising_edge(clk_i) then
-- No reset; logic is acyclic
scan_valid2(table_hi_idx) <= ts_scan_valid(table_hi_idx);
scan_valid3(table_hi_idx) <= -- beware of RW conflict on memory
f_eca_active_high(ts_manage_index(table_hi_idx) /= ts_scan_index(table_hi_idx));
scan_valid2(table_hi_idx) <= ts_scan_valid(table_hi_idx) and scan_valid3(table_hi_idx);
scan_time (table_hi_idx) <= ts_scan_time(table_hi_idx);
scan_valid1(table_hi_idx) <= scan_valid2(table_hi_idx);
......
modules/wr_eca/eca_pkg.vhd
View file @ 88dcf0ea
......@@ -184,12 +184,12 @@ package eca_pkg is
function f_eca_gray_decode(x : std_logic_vector; step : natural) return std_logic_vector;
-- Registers its inputs. Async outputs.
-- When r_clk_i=w_clk_i and r_addr_i=w_addr_i, r_data_o return old data (not w_data_i).
-- If r_clk_i /= w_clk_i, then r_data_o is undefined.
-- When r_addr_i=w_addr_i, r_data_o is undefined.
component eca_sdp is
generic(
g_addr_bits : natural := 8;
g_data_bits : natural := 8);
g_addr_bits : natural := 8;
g_data_bits : natural := 8;
g_dual_clock : boolean);
port(
r_clk_i : in std_logic;
r_addr_i : in std_logic_vector(g_addr_bits-1 downto 0);
......
modules/wr_eca/eca_sdp.vhd
View file @ 88dcf0ea
......@@ -27,16 +27,19 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.eca_pkg.all;
use work.genram_pkg.all;
-- Registers its inputs. Async outputs.
-- When r_clk_i=w_clk_i and r_addr_i=w_addr_i, r_data_o return old data (not w_data_i).
-- If r_clk_i /= w_clk_i, then r_data_o is undefined.
entity eca_sdp is
generic(
g_addr_bits : natural := 8;
g_data_bits : natural := 8);
g_addr_bits : natural := 8;
g_data_bits : natural := 8;
g_dual_clock : boolean);
port(
r_clk_i : in std_logic;
r_addr_i : in std_logic_vector(g_addr_bits-1 downto 0);
......@@ -48,27 +51,22 @@ entity eca_sdp is
end eca_sdp;
architecture rtl of eca_sdp is
type ram_t is array(2**g_addr_bits-1 downto 0) of
std_logic_vector(g_data_bits-1 downto 0);
signal ram : ram_t := (others => (others => '0'));
begin
r : process(r_clk_i)
begin
if rising_edge(r_clk_i) then
r_data_o <= ram(to_integer(unsigned(r_addr_i)));
end if;
end process;
w : process(w_clk_i)
begin
if rising_edge(w_clk_i) then
if w_en_i = '1' then
ram(to_integer(unsigned(w_addr_i))) <= w_data_i;
end if;
end if;
end process;
ram : generic_simple_dpram
generic map(
g_data_width => g_data_bits,
g_size => 2**g_addr_bits,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_dual_clock => g_dual_clock)
port map(
clka_i => w_clk_i,
wea_i => w_en_i,
aa_i => w_addr_i,
da_i => w_data_i,
clkb_i => r_clk_i,
ab_i => r_addr_i,
qb_o => r_data_o);
end rtl;
modules/wr_eca/eca_search.vhd
View file @ 88dcf0ea
......@@ -151,8 +151,9 @@ begin
Active : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_data_bits,
g_dual_clock => true)
port map(
r_clk_i => clk_i,
r_addr_i(s3_probe'length) => r3_page,
......@@ -170,8 +171,9 @@ begin
Program : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_data_bits,
g_dual_clock => false)
port map(
r_clk_i => t_clk_i,
r_addr_i(t_addr_i'length) => t_page_i,
......
modules/wr_eca/eca_walker.vhd
View file @ 88dcf0ea
......@@ -143,8 +143,9 @@ begin
Active : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_data_bits,
g_dual_clock => true)
port map(
r_clk_i => clk_i,
r_addr_i(s_w_addr'length) => s_w_page,
......@@ -166,8 +167,9 @@ begin
Program : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_data_bits,
g_dual_clock => false)
port map(
r_clk_i => t_clk_i,
r_addr_i(t_addr_i'length) => t_page_i,
......
modules/wr_eca/eca_wb_event.vhd
View file @ 88dcf0ea
......@@ -108,8 +108,9 @@ begin
Q : eca_sdp
generic map(
g_addr_bits => c_addr1_bits,
g_data_bits => 32)
g_addr_bits => c_addr1_bits,
g_data_bits => 32,
g_dual_clock => true)
port map(
r_clk_i => e_clk_i,
r_addr_i => std_logic_vector(se_addr),
......
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