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White Rabbit core collection
Commits
89b446bc
Commit
89b446bc
authored
Jul 17, 2012
by
Tomasz Wlostowski
Committed by
Grzegorz Daniluk
Mar 11, 2019
Browse files
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Plain Diff
wrsw_txtsu: re-generated WB slave using newer wbgen
parent
370b9503
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Showing
2 changed files
with
237 additions
and
242 deletions
+237
-242
wrsw_txtsu_wb.vhd
modules/wrsw_txtsu/wrsw_txtsu_wb.vhd
+226
-231
xwrsw_txtsu.vhd
modules/wrsw_txtsu/xwrsw_txtsu.vhd
+11
-11
No files found.
modules/wrsw_txtsu/wrsw_txtsu_wb.vhd
View file @
89b446bc
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrsw_txtsu_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_txtsu.wb
-- Created :
Fri Mar 16 15:01:36
2012
-- Created :
Thu Jul 12 12:01:11
2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_txtsu.wb
...
...
@@ -18,16 +18,17 @@ use work.wbgen2_pkg.all;
entity
wrsw_txtsu_wb
is
port
(
rst_n_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_ad
dr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat
a_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat
a_o
:
out
std_logic_vector
(
31
downto
0
);
clk_sys_i
:
in
std_logic
;
wb_ad
r_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat
_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat
_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_irq_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
-- FIFO write request
txtsu_tsf_wr_req_i
:
in
std_logic
;
-- FIFO full flag
...
...
@@ -45,6 +46,7 @@ end wrsw_txtsu_wb;
architecture
syn
of
wrsw_txtsu_wb
is
signal
txtsu_tsf_rst_n
:
std_logic
;
signal
txtsu_tsf_in_int
:
std_logic_vector
(
53
downto
0
);
signal
txtsu_tsf_out_int
:
std_logic_vector
(
53
downto
0
);
signal
txtsu_tsf_rdreq_int
:
std_logic
;
...
...
@@ -70,22 +72,20 @@ signal rwaddr_reg : std_logic_vector(2 downto 0);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
bus_clock_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg
<=
wb_dat
a
_i
;
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
bus_clock_int
<=
wb_clk_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
-- Main register bank access process.
process
(
bus_clock_int
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
...
...
@@ -95,7 +95,7 @@ begin
eic_ier_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
txtsu_tsf_rdreq_int
<=
'0'
;
elsif
rising_edge
(
bus_clock_int
)
then
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
...
...
@@ -113,256 +113,248 @@ begin
when
"000"
=>
if
(
wb_we_i
=
'1'
)
then
eic_idr_write_int
<=
'1'
;
else
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"001"
=>
if
(
wb_we_i
=
'1'
)
then
eic_ier_write_int
<=
'1'
;
else
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
0
)
<=
eic_imr_int
(
0
);
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
eic_imr_int
(
0
);
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011"
=>
if
(
wb_we_i
=
'1'
)
then
eic_isr_write_int
<=
'1'
;
else
rddata_reg
(
0
)
<=
eic_isr_status_int
(
0
);
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
eic_isr_status_int
(
0
);
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
if
(
txtsu_tsf_rdreq_int_d0
=
'0'
)
then
txtsu_tsf_rdreq_int
<=
not
txtsu_tsf_rdreq_int
;
else
if
(
txtsu_tsf_rdreq_int_d0
=
'0'
)
then
txtsu_tsf_rdreq_int
<=
not
txtsu_tsf_rdreq_int
;
else
rddata_reg
(
27
downto
0
)
<=
txtsu_tsf_out_int
(
27
downto
0
);
rddata_reg
(
31
downto
28
)
<=
txtsu_tsf_out_int
(
31
downto
28
);
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
if
;
rddata_reg
(
27
downto
0
)
<=
txtsu_tsf_out_int
(
27
downto
0
);
rddata_reg
(
31
downto
28
)
<=
txtsu_tsf_out_int
(
31
downto
28
);
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
if
;
when
"101"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
4
downto
0
)
<=
txtsu_tsf_out_int
(
36
downto
32
);
rddata_reg
(
31
downto
16
)
<=
txtsu_tsf_out_int
(
52
downto
37
);
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
end
if
;
rddata_reg
(
4
downto
0
)
<=
txtsu_tsf_out_int
(
36
downto
32
);
rddata_reg
(
31
downto
16
)
<=
txtsu_tsf_out_int
(
52
downto
37
);
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"110"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
0
)
<=
txtsu_tsf_out_int
(
53
);
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
0
)
<=
txtsu_tsf_out_int
(
53
);
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"111"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
16
)
<=
txtsu_tsf_full_int
;
rddata_reg
(
17
)
<=
txtsu_tsf_empty_int
;
rddata_reg
(
7
downto
0
)
<=
txtsu_tsf_usedw_int
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
rddata_reg
(
16
)
<=
txtsu_tsf_full_int
;
rddata_reg
(
17
)
<=
txtsu_tsf_empty_int
;
rddata_reg
(
7
downto
0
)
<=
txtsu_tsf_usedw_int
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
...
...
@@ -377,13 +369,14 @@ begin
-- Drive the data output bus
wb_dat
a
_o
<=
rddata_reg
;
wb_dat_o
<=
rddata_reg
;
-- extra code for reg/fifo/mem: Timestamp FIFO
txtsu_tsf_in_int
(
27
downto
0
)
<=
txtsu_tsf_val_r_i
;
txtsu_tsf_in_int
(
31
downto
28
)
<=
txtsu_tsf_val_f_i
;
txtsu_tsf_in_int
(
36
downto
32
)
<=
txtsu_tsf_pid_i
;
txtsu_tsf_in_int
(
52
downto
37
)
<=
txtsu_tsf_fid_i
;
txtsu_tsf_in_int
(
53
)
<=
txtsu_tsf_incorrect_i
;
txtsu_tsf_rst_n
<=
rst_n_i
;
txtsu_tsf_INST
:
wbgen2_fifo_sync
generic
map
(
g_size
=>
256
,
...
...
@@ -398,7 +391,8 @@ begin
rd_empty_o
=>
txtsu_tsf_empty_int
,
rd_usedw_o
=>
txtsu_tsf_usedw_int
,
rd_req_i
=>
txtsu_tsf_rdreq_int
,
clk_i
=>
bus_clock_int
,
rst_n_i
=>
txtsu_tsf_rst_n
,
clk_i
=>
clk_sys_i
,
wr_data_i
=>
txtsu_tsf_in_int
,
rd_data_o
=>
txtsu_tsf_out_int
);
...
...
@@ -447,7 +441,7 @@ begin
g_irq1f_mode
=>
0
)
port
map
(
clk_i
=>
bus_clock_int
,
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
irq_i
=>
irq_inputs_vector_int
,
irq_ack_o
=>
eic_irq_ack_int
,
...
...
@@ -459,16 +453,16 @@ begin
reg_isr_o
=>
eic_isr_status_int
,
reg_isr_i
=>
eic_isr_clear_int
,
reg_isr_wr_stb_i
=>
eic_isr_write_int
,
wb_irq_o
=>
wb_i
rq
_o
wb_irq_o
=>
wb_i
nt
_o
);
irq_inputs_vector_int
(
0
)
<=
irq_nempty_i
;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 0
process
(
bus_clock_int
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
txtsu_tsf_rdreq_int_d0
<=
'0'
;
elsif
rising_edge
(
bus_clock_int
)
then
elsif
rising_edge
(
clk_sys_i
)
then
txtsu_tsf_rdreq_int_d0
<=
txtsu_tsf_rdreq_int
;
end
if
;
end
process
;
...
...
@@ -476,7 +470,8 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 2
rwaddr_reg
<=
wb_addr_i
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
modules/wrsw_txtsu/xwrsw_txtsu.vhd
View file @
89b446bc
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-0
3-16
-- Last update: 2012-0
7-12
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -81,16 +81,16 @@ architecture syn of xwrsw_tx_tsu is
component
wrsw_txtsu_wb
port
(
rst_n_i
:
in
std_logic
;
wb_clk
_i
:
in
std_logic
;
wb_ad
d
r_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat
a
_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat
a
_o
:
out
std_logic_vector
(
31
downto
0
);
clk_sys
_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_i
rq
_o
:
out
std_logic
;
wb_i
nt
_o
:
out
std_logic
;
txtsu_tsf_wr_req_i
:
in
std_logic
;
txtsu_tsf_wr_full_o
:
out
std_logic
;
txtsu_tsf_wr_empty_o
:
out
std_logic
;
...
...
@@ -198,16 +198,16 @@ begin -- syn
U_WB_SLAVE
:
wrsw_txtsu_wb
port
map
(
rst_n_i
=>
rst_n_i
,
wb_clk
_i
=>
clk_sys_i
,
wb_ad
d
r_i
=>
wb_in
.
adr
(
2
downto
0
),
wb_dat
a
_i
=>
wb_in
.
dat
,
wb_dat
a
_o
=>
wb_out
.
dat
,
clk_sys
_i
=>
clk_sys_i
,
wb_adr_i
=>
wb_in
.
adr
(
2
downto
0
),
wb_dat_i
=>
wb_in
.
dat
,
wb_dat_o
=>
wb_out
.
dat
,
wb_cyc_i
=>
wb_in
.
cyc
,
wb_sel_i
=>
wb_in
.
sel
,
wb_stb_i
=>
wb_in
.
stb
,
wb_we_i
=>
wb_in
.
we
,
wb_ack_o
=>
wb_out
.
ack
,
wb_i
rq
_o
=>
wb_out
.
int
,
wb_i
nt
_o
=>
wb_out
.
int
,
txtsu_tsf_wr_req_i
=>
txtsu_tsf_wr_req
,
txtsu_tsf_wr_full_o
=>
txtsu_tsf_wr_full
,
txtsu_tsf_wr_empty_o
=>
txtsu_tsf_wr_empty
,
...
...
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