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White Rabbit core collection
Commits
370b9503
Commit
370b9503
authored
Mar 16, 2012
by
Tomasz Wlostowski
Committed by
Grzegorz Daniluk
Mar 11, 2019
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Plain Diff
modules/wrsw_txtsu: added support for invalid timestamp indication
parent
19764b0d
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4 changed files
with
134 additions
and
80 deletions
+134
-80
wrsw_txtsu.wb
modules/wrsw_txtsu/wrsw_txtsu.wb
+12
-3
wrsw_txtsu_pkg.vhd
modules/wrsw_txtsu/wrsw_txtsu_pkg.vhd
+5
-4
wrsw_txtsu_wb.vhd
modules/wrsw_txtsu/wrsw_txtsu_wb.vhd
+45
-4
xwrsw_txtsu.vhd
modules/wrsw_txtsu/xwrsw_txtsu.vhd
+72
-69
No files found.
modules/wrsw_txtsu/wrsw_txtsu.wb
View file @
370b9503
...
...
@@ -19,7 +19,8 @@ peripheral {
properly (there was no metastability/setup/hold violation)\
Entries also contain information required to identify the endpoint and frame for which the timestamp was taken:\
- FID - Frame identifier assigned by the NIC\
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames";
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames;\
- INCORRECT - timestamp may be incorrect, it has been generated during timebase adjustment";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
...
...
@@ -58,8 +59,16 @@ peripheral {
type = SLV;
size = 16;
align = 16;
};
};
};
field {
name = "Timestamp (possibly) incorrect";
description = "1: This timestamp may be incorrect (generated during PPS adjustment)\
0: Timestamp is correct.";
prefix = "incorrect";
type = BIT;
};
};
-- TXTSU interrupts
irq {
...
...
modules/wrsw_txtsu/wrsw_txtsu_pkg.vhd
View file @
370b9503
...
...
@@ -4,10 +4,11 @@ use ieee.std_logic_1164.all;
package
wrsw_txtsu_pkg
is
type
t_txtsu_timestamp
is
record
valid
:
std_logic
;
tsval
:
std_logic_vector
(
31
downto
0
);
port_id
:
std_logic_vector
(
5
downto
0
);
frame_id
:
std_logic_vector
(
15
downto
0
);
stb
:
std_logic
;
tsval
:
std_logic_vector
(
31
downto
0
);
port_id
:
std_logic_vector
(
5
downto
0
);
frame_id
:
std_logic_vector
(
15
downto
0
);
incorrect
:
std_logic
;
end
record
;
type
t_txtsu_timestamp_array
is
array
(
integer
range
<>
)
of
t_txtsu_timestamp
;
...
...
modules/wrsw_txtsu/wrsw_txtsu_wb.vhd
View file @
370b9503
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrsw_txtsu_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_txtsu.wb
-- Created :
Tue Jan 24 21:27:39
2012
-- Created :
Fri Mar 16 15:01:36
2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_txtsu.wb
...
...
@@ -38,14 +38,15 @@ entity wrsw_txtsu_wb is
txtsu_tsf_val_f_i
:
in
std_logic_vector
(
3
downto
0
);
txtsu_tsf_pid_i
:
in
std_logic_vector
(
4
downto
0
);
txtsu_tsf_fid_i
:
in
std_logic_vector
(
15
downto
0
);
txtsu_tsf_incorrect_i
:
in
std_logic
;
irq_nempty_i
:
in
std_logic
);
end
wrsw_txtsu_wb
;
architecture
syn
of
wrsw_txtsu_wb
is
signal
txtsu_tsf_in_int
:
std_logic_vector
(
5
2
downto
0
);
signal
txtsu_tsf_out_int
:
std_logic_vector
(
5
2
downto
0
);
signal
txtsu_tsf_in_int
:
std_logic_vector
(
5
3
downto
0
);
signal
txtsu_tsf_out_int
:
std_logic_vector
(
5
3
downto
0
);
signal
txtsu_tsf_rdreq_int
:
std_logic
;
signal
txtsu_tsf_rdreq_int_d0
:
std_logic
;
signal
eic_idr_int
:
std_logic_vector
(
0
downto
0
);
...
...
@@ -296,6 +297,44 @@ begin
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"110"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
0
)
<=
txtsu_tsf_out_int
(
53
);
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"111"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
16
)
<=
txtsu_tsf_full_int
;
...
...
@@ -344,10 +383,11 @@ begin
txtsu_tsf_in_int
(
31
downto
28
)
<=
txtsu_tsf_val_f_i
;
txtsu_tsf_in_int
(
36
downto
32
)
<=
txtsu_tsf_pid_i
;
txtsu_tsf_in_int
(
52
downto
37
)
<=
txtsu_tsf_fid_i
;
txtsu_tsf_in_int
(
53
)
<=
txtsu_tsf_incorrect_i
;
txtsu_tsf_INST
:
wbgen2_fifo_sync
generic
map
(
g_size
=>
256
,
g_width
=>
5
3
,
g_width
=>
5
4
,
g_usedw_size
=>
8
)
port
map
(
...
...
@@ -435,6 +475,7 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 2
rwaddr_reg
<=
wb_addr_i
;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
...
...
modules/wrsw_txtsu/xwrsw_txtsu.vhd
View file @
370b9503
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-0
1-20
-- Last update: 2012-0
3-16
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -66,8 +66,8 @@ entity xwrsw_tx_tsu is
-- Wishbone bus
-------------------------------------------------------------------------------
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
);
...
...
@@ -77,42 +77,43 @@ end xwrsw_tx_tsu;
architecture
syn
of
xwrsw_tx_tsu
is
component
wrsw_txtsu_wb
port
(
rst_n_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_irq_o
:
out
std_logic
;
txtsu_tsf_wr_req_i
:
in
std_logic
;
txtsu_tsf_wr_full_o
:
out
std_logic
;
txtsu_tsf_wr_empty_o
:
out
std_logic
;
txtsu_tsf_val_r_i
:
in
std_logic_vector
(
27
downto
0
);
txtsu_tsf_val_f_i
:
in
std_logic_vector
(
3
downto
0
);
txtsu_tsf_pid_i
:
in
std_logic_vector
(
4
downto
0
);
txtsu_tsf_fid_i
:
in
std_logic_vector
(
15
downto
0
);
irq_nempty_i
:
in
std_logic
);
rst_n_i
:
in
std_logic
;
wb_clk_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_irq_o
:
out
std_logic
;
txtsu_tsf_wr_req_i
:
in
std_logic
;
txtsu_tsf_wr_full_o
:
out
std_logic
;
txtsu_tsf_wr_empty_o
:
out
std_logic
;
txtsu_tsf_val_r_i
:
in
std_logic_vector
(
27
downto
0
);
txtsu_tsf_val_f_i
:
in
std_logic_vector
(
3
downto
0
);
txtsu_tsf_pid_i
:
in
std_logic_vector
(
4
downto
0
);
txtsu_tsf_fid_i
:
in
std_logic_vector
(
15
downto
0
);
txtsu_tsf_incorrect_i
:
in
std_logic
;
irq_nempty_i
:
in
std_logic
);
end
component
;
signal
txtsu_tsf_wr_req
:
std_logic
;
signal
txtsu_tsf_wr_full
:
std_logic
;
signal
txtsu_tsf_wr_empty
:
std_logic
;
signal
txtsu_tsf_val_r
:
std_logic_vector
(
27
downto
0
);
signal
txtsu_tsf_val_f
:
std_logic_vector
(
3
downto
0
);
signal
txtsu_tsf_pid
:
std_logic_vector
(
4
downto
0
);
signal
txtsu_tsf_fid
:
std_logic_vector
(
15
downto
0
);
signal
txtsu_tsf_wr_req
:
std_logic
;
signal
txtsu_tsf_wr_full
:
std_logic
;
signal
txtsu_tsf_wr_empty
:
std_logic
;
signal
txtsu_tsf_val_r
:
std_logic_vector
(
27
downto
0
);
signal
txtsu_tsf_val_f
:
std_logic_vector
(
3
downto
0
);
signal
txtsu_tsf_pid
:
std_logic_vector
(
4
downto
0
);
signal
txtsu_tsf_fid
:
std_logic_vector
(
15
downto
0
);
signal
txtsu_tsf_incorrect
:
std_logic
;
signal
irq_nempty
:
std_logic
;
signal
scan_cntr
:
unsigned
(
4
downto
0
);
signal
scan_cntr
:
unsigned
(
4
downto
0
);
type
t_txtsu_state
is
(
TSU_SCAN
,
TSU_ACK
);
...
...
@@ -120,8 +121,8 @@ architecture syn of xwrsw_tx_tsu is
signal
cur_ep
:
integer
;
signal
wb_out
:
t_wishbone_slave_out
;
signal
wb_in
:
t_wishbone_slave_in
;
signal
wb_out
:
t_wishbone_slave_out
;
signal
wb_in
:
t_wishbone_slave_in
;
begin
-- syn
...
...
@@ -134,12 +135,12 @@ begin -- syn
g_slave_mode
=>
g_interface_mode
,
g_slave_granularity
=>
g_address_granularity
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
master_i
=>
wb_out
,
master_o
=>
wb_in
,
slave_i
=>
wb_i
,
slave_o
=>
wb_o
);
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
master_i
=>
wb_out
,
master_o
=>
wb_in
,
slave_i
=>
wb_i
,
slave_o
=>
wb_o
);
cur_ep
<=
to_integer
(
scan_cntr
);
...
...
@@ -159,16 +160,17 @@ begin -- syn
case
state
is
when
TSU_SCAN
=>
if
(
timestamps_i
(
cur_ep
)
.
valid
=
'1'
)
then
if
(
timestamps_i
(
cur_ep
)
.
stb
=
'1'
)
then
timestamps_ack_o
(
cur_ep
)
<=
'1'
;
state
<=
TSU_ACK
;
state
<=
TSU_ACK
;
if
(
txtsu_tsf_wr_full
=
'0'
)
then
txtsu_tsf_pid
<=
timestamps_i
(
cur_ep
)
.
port_id
(
4
downto
0
);
txtsu_tsf_fid
<=
timestamps_i
(
cur_ep
)
.
frame_id
;
txtsu_tsf_val_f
<=
timestamps_i
(
cur_ep
)
.
tsval
(
31
downto
28
);
txtsu_tsf_val_r
<=
timestamps_i
(
cur_ep
)
.
tsval
(
27
downto
0
);
txtsu_tsf_wr_req
<=
'1'
;
txtsu_tsf_pid
<=
timestamps_i
(
cur_ep
)
.
port_id
(
4
downto
0
);
txtsu_tsf_fid
<=
timestamps_i
(
cur_ep
)
.
frame_id
;
txtsu_tsf_val_f
<=
timestamps_i
(
cur_ep
)
.
tsval
(
31
downto
28
);
txtsu_tsf_val_r
<=
timestamps_i
(
cur_ep
)
.
tsval
(
27
downto
0
);
txtsu_tsf_incorrect
<=
timestamps_i
(
cur_ep
)
.
incorrect
;
txtsu_tsf_wr_req
<=
'1'
;
end
if
;
else
if
(
scan_cntr
=
g_num_ports
-1
)
then
...
...
@@ -178,9 +180,9 @@ begin -- syn
end
if
;
end
if
;
when
TSU_ACK
=>
timestamps_ack_o
(
cur_ep
)
<=
'0'
;
txtsu_tsf_wr_req
<=
'0'
;
state
<=
TSU_SCAN
;
timestamps_ack_o
(
cur_ep
)
<=
'0'
;
txtsu_tsf_wr_req
<=
'0'
;
state
<=
TSU_SCAN
;
if
(
scan_cntr
=
g_num_ports
-1
)
then
scan_cntr
<=
(
others
=>
'0'
);
else
...
...
@@ -195,25 +197,26 @@ begin -- syn
U_WB_SLAVE
:
wrsw_txtsu_wb
port
map
(
rst_n_i
=>
rst_n_i
,
wb_clk_i
=>
clk_sys_i
,
wb_addr_i
=>
wb_in
.
adr
(
2
downto
0
),
wb_data_i
=>
wb_in
.
dat
,
wb_data_o
=>
wb_out
.
dat
,
wb_cyc_i
=>
wb_in
.
cyc
,
wb_sel_i
=>
wb_in
.
sel
,
wb_stb_i
=>
wb_in
.
stb
,
wb_we_i
=>
wb_in
.
we
,
wb_ack_o
=>
wb_out
.
ack
,
wb_irq_o
=>
wb_out
.
int
,
txtsu_tsf_wr_req_i
=>
txtsu_tsf_wr_req
,
txtsu_tsf_wr_full_o
=>
txtsu_tsf_wr_full
,
txtsu_tsf_wr_empty_o
=>
txtsu_tsf_wr_empty
,
txtsu_tsf_val_r_i
=>
txtsu_tsf_val_r
,
txtsu_tsf_val_f_i
=>
txtsu_tsf_val_f
,
txtsu_tsf_pid_i
=>
txtsu_tsf_pid
,
txtsu_tsf_fid_i
=>
txtsu_tsf_fid
,
irq_nempty_i
=>
irq_nempty
);
rst_n_i
=>
rst_n_i
,
wb_clk_i
=>
clk_sys_i
,
wb_addr_i
=>
wb_in
.
adr
(
2
downto
0
),
wb_data_i
=>
wb_in
.
dat
,
wb_data_o
=>
wb_out
.
dat
,
wb_cyc_i
=>
wb_in
.
cyc
,
wb_sel_i
=>
wb_in
.
sel
,
wb_stb_i
=>
wb_in
.
stb
,
wb_we_i
=>
wb_in
.
we
,
wb_ack_o
=>
wb_out
.
ack
,
wb_irq_o
=>
wb_out
.
int
,
txtsu_tsf_wr_req_i
=>
txtsu_tsf_wr_req
,
txtsu_tsf_wr_full_o
=>
txtsu_tsf_wr_full
,
txtsu_tsf_wr_empty_o
=>
txtsu_tsf_wr_empty
,
txtsu_tsf_val_r_i
=>
txtsu_tsf_val_r
,
txtsu_tsf_val_f_i
=>
txtsu_tsf_val_f
,
txtsu_tsf_pid_i
=>
txtsu_tsf_pid
,
txtsu_tsf_fid_i
=>
txtsu_tsf_fid
,
txtsu_tsf_incorrect_i
=>
txtsu_tsf_incorrect
,
irq_nempty_i
=>
irq_nempty
);
irq_nempty
<=
not
txtsu_tsf_wr_empty
;
...
...
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