wr_endpoint: ep_rx_bypass_queue: added use for Xilinx libraries (shiftreg to be…

wr_endpoint: ep_rx_bypass_queue: added use for Xilinx libraries (shiftreg to be moved to general-cores)

wr_endpoint: ep_rx_bypass_queue: added use for Xilinx libraries (shiftreg to be…
wr_endpoint: ep_rx_bypass_queue: added use for Xilinx libraries (shiftreg to be moved to general-cores)
8b7d96f9 · Tomasz Wlostowski · b2edc7ba · 8b7d96f9
Commit 8b7d96f9 authored Oct 25, 2011 by Tomasz Wlostowski
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ep_rx_bypass_queue.vhd modules/wr_endpoint/ep_rx_bypass_queue.vhd +9 -1

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--- a/modules/wr_endpoint/ep_rx_bypass_queue.vhd
+++ b/modules/wr_endpoint/ep_rx_bypass_queue.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2011-08-10
-- Last update: 2011-10-18
+-- Last update: 2011-10-25
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -153,10 +153,18 @@ begin  -- behavioral
  
 end behavioral;

+
+-------------------------------------------------------------------------------
+--FIXME: Generic-ize THIS!
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

+library unisim;
+use unisim.vcomponents.all;
+
 entity ep_shift_reg is
  generic(g_size : integer := 16);
  port(