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White Rabbit core collection
Commit 8bc233d9 authored by Mathias Kreider's avatar Mathias Kreider
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tlu: udp fix for tlu-ctl pop functions

parent 4177c4b6
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Showing with 53 additions and 34 deletions
modules/wr_tlu/lib/hw-tlu.h
View file @ 8bc233d9
#define GSI_VENDOR_ID 0x651
#define TLU_DEVICE_ID 0x10051981U
//1 pop => (3rd+rec+adr + 1wr+rec+adr))* 4bytes = 32bytes
#define POP_TS_OPSIZE 32
#define UDP_MAX_POPS 46 // 1500 / 32
#define TLU_READY 0x00 //
#define TLU_CLEAR 0x04
#define TLU_TEST 0x08
......
modules/wr_tlu/lib/tlu.cpp
View file @ 8bc233d9
......@@ -407,6 +407,7 @@ status_t TLU::pop_all(int channel, std::vector<uint64_t>& queue) {
std::vector<Element> elements;
data_t fill;
uint64_t time;
uint16_t chunks;
if (channel < 0 || channel >= (int)channels.size())
return EB_FAIL;
......@@ -425,20 +426,26 @@ status_t TLU::pop_all(int channel, std::vector<uint64_t>& queue) {
elements.resize(fill);
if (fill == 0) return EB_OK;
if ((status = cycle.open(device)) != EB_OK)
return status;
chunks = fill / UDP_MAX_POPS + unsigned(bool(fill % UDP_MAX_POPS));
cycle.write(address + TLU_CH_SELECT, EB_DATA32, channel);
for (unsigned i = 0; i < elements.size(); ++i) {
Element& e = elements[i];
cycle.read (address + TLU_CH_TIME1, EB_DATA32, &e.time1);
cycle.read (address + TLU_CH_TIME0, EB_DATA32, &e.time0);
cycle.read (address + TLU_CH_SUB, EB_DATA32, &e.sub);
cycle.write(address + TLU_CH_POP, EB_DATA32, 1);
}
for (unsigned j = 0; j < chunks; j++)
{
if ((status = cycle.open(device)) != EB_OK)
return status;
cycle.write(address + TLU_CH_SELECT, EB_DATA32, channel);
for (unsigned i = j*UDP_MAX_POPS; i < std::min(unsigned(fill), (j+1)*UDP_MAX_POPS); i++)
{
Element& e = elements[i];
cycle.read (address + TLU_CH_TIME1, EB_DATA32, &e.time1);
cycle.read (address + TLU_CH_TIME0, EB_DATA32, &e.time0);
cycle.read (address + TLU_CH_SUB, EB_DATA32, &e.sub);
cycle.write(address + TLU_CH_POP, EB_DATA32, 1);
}
if ((status = cycle.close()) != EB_OK)
return status;
if ((status = cycle.close()) != EB_OK)
return status;
}
for (unsigned i = 0; i < elements.size(); ++i) {
Element& e = elements[i];
......@@ -462,6 +469,7 @@ status_t TLU::pop_all(std::vector<std::vector<uint64_t> >& queues) {
std::vector<std::vector<Element> > elements;
std::vector<data_t> fill;
uint64_t time;
uint16_t chunks;
queues.resize(channels.size());
fill.resize(channels.size());
......@@ -476,27 +484,33 @@ status_t TLU::pop_all(std::vector<std::vector<uint64_t> >& queues) {
if ((status = cycle.close()) != EB_OK)
return status;
if ((status = cycle.open(device)) != EB_OK)
return status;
elements.resize(channels.size());
for (unsigned c = 0; c < channels.size(); ++c) {
std::vector<Element>& esv = elements[c];
esv.resize(fill[c]);
cycle.write(address + TLU_CH_SELECT, EB_DATA32, c);
for (unsigned e = 0; e < esv.size(); ++e) {
Element& es = esv[e];
cycle.read (address + TLU_CH_TIME1, EB_DATA32, &es.time1);
cycle.read (address + TLU_CH_TIME0, EB_DATA32, &es.time0);
cycle.read (address + TLU_CH_SUB, EB_DATA32, &es.sub);
cycle.write(address + TLU_CH_POP, EB_DATA32, 1);
}
}
if ((status = cycle.close()) != EB_OK)
return status;
elements.resize(channels.size());
for (unsigned c = 0; c < channels.size(); ++c) {
std::vector<Element>& esv = elements[c];
esv.resize(fill[c]);
chunks = fill[c] / UDP_MAX_POPS + unsigned(bool(fill[c] % UDP_MAX_POPS));
for (unsigned j = 0; j < chunks; j++)
{
if ((status = cycle.open(device)) != EB_OK)
return status;
cycle.write(address + TLU_CH_SELECT, EB_DATA32, c);
for (unsigned e = j*UDP_MAX_POPS; e < std::min(unsigned(fill[c]), (j+1)*UDP_MAX_POPS); e++) {
Element& es = esv[e];
cycle.read (address + TLU_CH_TIME1, EB_DATA32, &es.time1);
cycle.read (address + TLU_CH_TIME0, EB_DATA32, &es.time0);
cycle.read (address + TLU_CH_SUB, EB_DATA32, &es.sub);
cycle.write(address + TLU_CH_POP, EB_DATA32, 1);
}
if ((status = cycle.close()) != EB_OK)
return status;
}
}
for (unsigned c = 0; c < channels.size(); ++c) {
std::vector<uint64_t>& o = queues[c];
std::vector<Element>& esv = elements[c];
......
modules/wr_tlu/tlu.h
View file @ 8bc233d9
......@@ -70,7 +70,7 @@ struct TLU {
/* Access/modify the underlying hardware */
/* ------------------------------------------------------------------- */
Device device; /* Device which hosts this ECA */
Device device; /* Device which hosts this TLU */
eb_address_t address; /* Wishbone base address */
/* Reload mutable registers from hardware */
......
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