top/vfchd: move ext PPS input to fmc-dio4

8c21df1d · Dimitris Lampridis · 29c5a52e · 8c21df1d · 8c21df1d
Commit 8c21df1d authored Feb 23, 2017 by Dimitris Lampridis
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Showing with 18 additions and 11 deletions

quartus_preflow.tcl syn/vfchd_ref_design/quartus_preflow.tcl +7 -3

vfchd_wr_ref_top.vhd top/vfchd_ref_design/vfchd_wr_ref_top.vhd +11 -8

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--- a/syn/vfchd_ref_design/quartus_preflow.tcl
+++ b/syn/vfchd_ref_design/quartus_preflow.tcl
@@ -208,13 +208,17 @@ loc AU28 vme_addr_b[31]
 loc AM27 fmc_enable_n_o
 loc C20  dio_led_term_o
 loc D20  dio_led_out_o
-loc M27  dio1_i "LVDS"
+loc D25  dio4_i "LVDS"
+# VFC-HD has a discrete diff receiver for the FMC-DIO clock
+# so the signal arrives to the FPGA as CMOS (single-ended)
 loc AK34 dio5_clk_i
-loc R26  dio1_oe_n_o
+loc M29  dio4_oe_n_o
 loc C28  dio5_oe_n_o
-loc T27  dio1_term_en_o
+loc B27  dio4_term_en_o
 loc C27  dio5_term_en_o

+loc AH21 vfchd_gpio1_o
+loc AG21 vfchd_gpio2_o
 loc AL26 vfchd_gpio3_o
 loc AV24 vfchd_gpio4_o


--- a/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
+++ b/top/vfchd_ref_design/vfchd_wr_ref_top.vhd
@@ -151,9 +151,9 @@ entity vfchd_wr_ref_top is
    fmc_enable_n_o : out std_logic;
    dio_led_term_o : out std_logic;
    dio_led_out_o  : out std_logic;
-    dio1_i         : in  std_logic;   -- LEMO1 as input for ext PPS in
-    dio1_oe_n_o    : out std_logic;   -- LEMO1 output enable control
-    dio1_term_en_o : out std_logic;   -- LEMO1 output termination control
+    dio4_i         : in  std_logic;   -- LEMO4 as input for ext PPS in
+    dio4_oe_n_o    : out std_logic;   -- LEMO4 output enable control
+    dio4_term_en_o : out std_logic;   -- LEMO4 output termination control
    dio5_clk_i     : in  std_logic;   -- LEMO5 clock input for ext 10MHz
    dio5_oe_n_o    : out std_logic;   -- LEMO5 output enable control
    dio5_term_en_o : out std_logic;   -- LEMO5 output termination control
@@ -256,6 +256,7 @@ architecture top of vfchd_wr_ref_top is
  signal rst_sys_62m5_n : std_logic;
  signal clk_ref_125m   : std_logic;
  signal clk_ref_div2   : std_logic;
+  signal clk_ext_ref    : std_logic;

  -- I2C EEPROM
  signal eeprom_sda_in  : std_logic;
@@ -313,6 +314,7 @@ architecture top of vfchd_wr_ref_top is
  -- LEDs
  signal pps_led     : std_logic;
  signal pps_led_d   : std_logic;
+  signal pps_ext_in  : std_logic;
  signal vfchd_led   : std_logic_vector(7 downto 0);
  signal wr_led_link : std_logic;
  signal wr_led_act  : std_logic;
@@ -401,7 +403,7 @@ begin  -- architecture top
    port map (
      clk_board_125m_i  => clk_board_125m_i,
      clk_board_20m_i   => clk_board_20m_i,
-      clk_ext_10m_i     => dio5_clk_i,
+      clk_ext_10m_i     => clk_ext_ref,
      areset_n_i        => areset_n_i,
      clk_sys_62m5_o    => clk_sys_62m5,
      clk_ref_125m_o    => clk_ref_125m,
@@ -427,7 +429,7 @@ begin  -- architecture top
      wb_slave_i        => cnx1_slave_in(c_WB_SLAVE_WRC),
      wb_eth_master_o   => cnx1_master_out(c_WB_MASTER_ETHBONE),
      wb_eth_master_i   => cnx1_master_in(c_WB_MASTER_ETHBONE),
-      pps_ext_i         => dio1_i,
+      pps_ext_i         => pps_ext_in,
      pps_p_o           => vfchd_gpio3_o,
      pps_led_o         => pps_led,
      led_link_o        => wr_led_link,
@@ -689,11 +691,12 @@ begin  -- architecture top
  vfchd_gpio4_o <= clk_ref_div2;

  -- Configure DIO LEMO1 and LEMO5 as inputs
-  dio1_term_en_o <= '0';
-  dio1_oe_n_o    <= '1';
+  dio4_term_en_o <= '0';
+  dio4_oe_n_o    <= '1';
+  pps_ext_in     <= dio4_i;
  dio5_term_en_o <= '0';
  dio5_oe_n_o    <= '1';
-
+  clk_ext_ref    <= dio5_clk_i;
  dio_led_term_o <= '0';
  dio_led_out_o  <= pps_led_d;