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White Rabbit core collection
Commit 8e6ca147 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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altera: use wishbone to program fpga's spi boot flash 

also, the datasheet says our new flash chips are only good to 33MHz
with slow reads. change quartus fpga load config to 20MHz (not 40).
parent aa9b79cb
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Showing with 148 additions and 317 deletions
platform/altera/Manifest.py
View file @ 8e6ca147
files = [ "altera_pkg.vhd", "flash_loader.vhd", "pow_reset.vhd" ]
files = [ "altera_pkg.vhd" ]
modules = {"local": [ "wr_gxb_phy_arria2", "dmtd_pll", "ref_pll", "sys_pll" ] }
platform/altera/altera_pkg.vhd
View file @ 8e6ca147
......@@ -3,19 +3,6 @@ use ieee.std_logic_1164.all;
package wr_altera_pkg is
component flash_loader
port (
noe_in : in std_logic
);
end component;
component pow_reset is
port (
clk : in std_logic; -- 125Mhz
nreset : buffer std_logic
);
end component;
component dmtd_pll
port
(
......@@ -38,11 +25,9 @@ package wr_altera_pkg is
port
(
inclk0 : in std_logic := '0'; -- 125 MHz
c0 : out std_logic; -- 125 MHz
c0 : out std_logic; -- 62.5 MHz
c1 : out std_logic; -- 50 MHz
c2 : out std_logic; -- 62.5 MHz
c3 : out std_logic; -- 20 MHz
c4 : out std_logic; -- 100 MHz
c2 : out std_logic; -- 20 MHz
locked : out std_logic
);
end component;
......
platform/altera/flash_loader.vhd deleted 100644 → 0
View file @ aa9b79cb
-- megafunction wizard: %Serial Flash Loader%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altserial_flash_loader
-- ============================================================
-- File Name: flash_loader.vhd
-- Megafunction Name(s):
-- altserial_flash_loader
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY flash_loader IS
PORT
(
noe_in : IN STD_LOGIC
);
END flash_loader;
ARCHITECTURE SYN OF flash_loader IS
COMPONENT altserial_flash_loader
GENERIC (
enable_quad_spi_support : NATURAL;
enable_shared_access : STRING;
enhanced_mode : NATURAL;
intended_device_family : STRING;
lpm_type : STRING
);
PORT (
noe : IN STD_LOGIC
);
END COMPONENT;
BEGIN
altserial_flash_loader_component : altserial_flash_loader
GENERIC MAP (
enable_quad_spi_support => 0,
enable_shared_access => "OFF",
enhanced_mode => 1,
intended_device_family => "Arria II GX",
lpm_type => "altserial_flash_loader"
)
PORT MAP (
noe => noe_in
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
platform/altera/pow_reset.vhd deleted 100644 → 0
View file @ aa9b79cb
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pow_reset is
port (
clk : in std_logic; -- 125Mhz
nreset : buffer std_logic
);
end entity;
architecture pow_reset_arch of pow_reset is
signal powerOn : unsigned(6 downto 0) := "0000000"; -- 7Bit for 1ms nrst
begin
nres : process(Clk)
begin
if Clk'event and Clk = '1' then
if nreset = '0' then
powerOn <= powerOn + 1;
end if;
nReset <= std_logic(powerOn(powerON'high));
end if;
end process;
end architecture;
platform/altera/sys_pll/sys_pll.cmp
View file @ 8e6ca147
--Copyright (C) 1991-2011 Altera Corporation
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
......@@ -20,8 +20,6 @@ component sys_pll
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
platform/altera/sys_pll/sys_pll.ppf
View file @ 8e6ca147
......@@ -6,8 +6,6 @@
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="c3" direction="output" scope="external" source="clock" />
<pin name="c4" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
......
platform/altera/sys_pll/sys_pll.qip
View file @ 8e6ca147
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name IP_TOOL_VERSION "12.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sys_pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys_pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys_pll.ppf"]
platform/altera/sys_pll/sys_pll.vhd
View file @ 8e6ca147
This diff is collapsed.
syn/gsi_exploder/wr_core_demo/exploder_top.qsf
View file @ 8e6ca147
......@@ -29,7 +29,7 @@ set_global_assignment -rise -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO"
set_global_assignment -fall -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO"
set_global_assignment -rise -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING"
set_global_assignment -fall -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_20MHZ
set_location_assignment PIN_C4 -to any_i[1]
set_location_assignment PIN_B4 -to any_i[2]
set_location_assignment PIN_D9 -to any_i[3]
......@@ -414,8 +414,6 @@ set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wrc_syscon_wb.vh
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wrc_syscon_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/xwr_syscon_wb.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/altera_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/flash_loader.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/pow_reset.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/wr_gxb_phy_arria2/altgx_reconf.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/wr_gxb_phy_arria2/arria_phy.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/wr_gxb_phy_arria2/rxclkout.vhd
......@@ -493,30 +491,30 @@ set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_reconfig.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie_serdes.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie_core.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_32to64.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_64to32.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_altera.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_tlp.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_wb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_wb_pkg.vhd
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_reconfig.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_pcie_serdes.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_pcie_core.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_pcie.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
......@@ -541,6 +539,6 @@ set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_us
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd
set_global_assignment -name SDC_FILE ../../../top/gsi_exploder/wr_core_demo/exploder_top.sdc
set_global_assignment -name SDC_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie.sdc
set_global_assignment -name SDC_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_pcie.sdc
syn/gsi_scu/wr_core_demo/scu.qsf
View file @ 8e6ca147
......@@ -21,7 +21,7 @@ set_global_assignment -rise -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO"
set_global_assignment -fall -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO"
set_global_assignment -rise -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING"
set_global_assignment -fall -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_20MHZ
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_Y10 -to nres
......@@ -711,7 +711,7 @@ set_location_assignment PIN_C27 -to A_MASTER_CON_RX[1]
set_location_assignment PIN_D25 -to QL2_REFCLK6p
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to lemo_io1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to lemo_io2
set_global_assignment -name SEARCH_PATH "../../../ip_cores/general-cores/modules/wishbone/wb_pcie/ip_compiler_for_pci_express-library/"
set_global_assignment -name SEARCH_PATH "../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/"
set_location_assignment PIN_E27 -to sfp2_ref_clk_i
set_instance_assignment -name IO_STANDARD LVDS -to sfp2_ref_clk_i
set_location_assignment PIN_E28 -to "sfp2_ref_clk_i(n)"
......@@ -813,8 +813,6 @@ set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wrc_syscon_wb.vh
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/wrc_syscon_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wrc_core/xwr_syscon_wb.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/altera_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/flash_loader.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/pow_reset.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/wr_gxb_phy_arria2/altgx_reconf.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/wr_gxb_phy_arria2/arria_phy.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/wr_gxb_phy_arria2/rxclkout.vhd
......@@ -892,30 +890,30 @@ set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_reconfig.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie_serdes.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie_core.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_32to64.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_64to32.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_altera.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_tlp.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_wb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/pcie_wb_pkg.vhd
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_reconfig.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_pcie_serdes.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_pcie_core.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_pcie.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd
set_global_assignment -name VERILOG_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
......@@ -940,6 +938,6 @@ set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_us
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd
set_global_assignment -name VHDL_FILE ../../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd
set_global_assignment -name SDC_FILE ../../../top/gsi_scu/wr_core_demo/scu_top.sdc
set_global_assignment -name SDC_FILE ../../../ip_cores/general-cores/modules/wishbone/wb_pcie/altera_pcie.sdc
set_global_assignment -name SDC_FILE ../../../ip_cores/general-cores/platform/altera/wb_pcie/altera_pcie.sdc
top/gsi_exploder/wr_core_demo/exploder_top.vhd
View file @ 8e6ca147
......@@ -2,15 +2,15 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
library work;
use work.wishbone_pkg.all;
use work.wb_cores_pkg_gsi.all;
use work.eca_pkg.all;
use work.wr_altera_pkg.all;
use work.altera_flash_pkg.all;
use work.etherbone_pkg.all;
use work.ez_usb_pkg.all;
......@@ -306,7 +306,6 @@ entity exploder_top is
-- nimin_i(6) -- AB7 N60 94
-- nimin_i(7) -- U9 P61 98
-- nimin_i(8) -- V9 N61 100
end exploder_top;
architecture rtl of exploder_top is
......@@ -315,14 +314,15 @@ architecture rtl of exploder_top is
constant c_wrcore_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Top crossbar layout
constant c_slaves : natural := 5;
constant c_slaves : natural := 6;
constant c_masters : natural := 3;
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
(0 => f_sdb_embed_bridge(c_wrcore_bridge_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_wb_timestamp_latch_sdb, x"00100000"),
2 => f_sdb_embed_device(c_eca_sdb, x"00100800"),
3 => f_sdb_embed_device(c_eca_evt_sdb, x"00100C00"),
4 => f_sdb_embed_device(c_wb_serial_lcd_sdb, x"00100D00"));
4 => f_sdb_embed_device(c_wb_serial_lcd_sdb, x"00100D00"),
5 => f_sdb_embed_device(c_wb_spi_flash_sdb, x"01000000"));
constant c_sdb_address : t_wishbone_address := x"00300000";
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
......@@ -335,10 +335,16 @@ architecture rtl of exploder_top is
-- Sys PLL from clk_125m_local_i
signal sys_locked : std_logic;
signal clk_reconf : std_logic;
signal clk_62_5 : std_logic;
signal clk_50 : std_logic;
signal clk_20 : std_logic;
signal rstn_sys : std_logic;
-- logical clock names
signal clk_sys : std_logic;
signal clk_reconf : std_logic;
signal clk_flash : std_logic;
signal clk_lcd : std_logic;
signal rstn_sys : std_logic;
-- RX PLL
signal gxb_locked : std_logic;
......@@ -435,10 +441,6 @@ begin
sfp1_mod1_io <= '0' when sfp1_scl_o = '0' else 'Z';
sfp1_mod2_io <= '0' when sfp1_sda_o = '0' else 'Z';
Inst_flash_loader_v01 : flash_loader
port map(
noe_in => '0');
dmtd_inst : dmtd_pll port map(
inclk0 => clk_20m_vcxo_i, -- 20 Mhz
c0 => clk_dmtd, -- 62.5MHz
......@@ -451,19 +453,22 @@ begin
sys_inst : sys_pll port map(
inclk0 => clk_125m_local_i, -- 125 Mhz
c0 => open, -- 125 MHz
c1 => clk_reconf, -- 50 Mhz
c2 => clk_sys, -- 62.5MHz
c3 => clk_lcd, -- 20 MHz
c4 => open, -- 100 MHz
c0 => clk_62_5, -- 62.5 MHz
c1 => clk_50, -- 50 Mhz
c2 => clk_20, -- 20 MHz
locked => sys_locked);
clk_sys <= clk_62_5;
clk_reconf <= clk_50;
clk_flash <= clk_50;
clk_lcd <= clk_20;
sys_reset : gc_reset
generic map(
g_clocks => 1,
g_logdelay => 19) -- 8.4ms at 62.5MHz (must exceed 5ms for USB)
port map(
free_clk_i => clk_sys,
free_clk_i => clk_62_5,
locked_i => sys_locked,
clks_i(0) => clk_sys,
rstn_o(0) => rstn_sys);
......@@ -478,6 +483,22 @@ begin
clks_i(0) => clk_ref,
rstn_o(0) => rstn_ref);
flash : flash_top
generic map(
g_family => "Arria II GX",
g_port_width => 1, -- single-lane SPI bus
g_addr_width => 24, -- 3 byte addressed chip
g_input_latch_edge => '1', -- 30ns at 50MHz (10+20) after falling edge sets up SPI output
g_output_latch_edge => '0', -- falling edge to meet SPI setup times
g_input_to_output_cycles => 2) -- delayed to work-around unconstrained design
port map(
clk_i => clk_sys,
rstn_i => rstn_sys,
slave_i => cbar_master_o(5),
slave_o => cbar_master_i(5),
clk_out_i => clk_flash,
clk_in_i => clk_flash); -- no need to phase shift at 50MHz
rstn_wr <= rstn_sys and gxb_locked;
U_WR_CORE : xwr_core
generic map (
......
top/gsi_scu/wr_core_demo/scu_top.vhd
View file @ 8e6ca147
......@@ -2,17 +2,17 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
library work;
use work.wishbone_pkg.all;
use work.eca_pkg.all;
use work.wb_cores_pkg_gsi.all;
use work.pcie_wb_pkg.all;
use work.wr_altera_pkg.all;
use work.etherbone_pkg.all;
use work.altera_flash_pkg.all;
entity scu_top is
port(
......@@ -189,13 +189,14 @@ architecture rtl of scu_top is
constant c_wrcore_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Top crossbar layout
constant c_slaves : natural := 4;
constant c_slaves : natural := 5;
constant c_masters : natural := 2;
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
(0 => f_sdb_embed_bridge(c_wrcore_bridge_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_wb_timestamp_latch_sdb, x"00100000"),
2 => f_sdb_embed_device(c_eca_sdb, x"00100800"),
3 => f_sdb_embed_device(c_eca_evt_sdb, x"00100C00"));
3 => f_sdb_embed_device(c_eca_evt_sdb, x"00100C00"),
4 => f_sdb_embed_device(c_wb_spi_flash_sdb, x"01000000"));
constant c_sdb_address : t_wishbone_address := x"00300000";
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
......@@ -208,11 +209,17 @@ architecture rtl of scu_top is
-- Sys PLL from clk_125m_local_i
signal sys_locked : std_logic;
signal clk_62_5 : std_logic;
signal clk_50 : std_logic;
signal clk_20 : std_logic;
signal rstn_sys : std_logic;
-- logical clock names
signal clk_pcie : std_logic;
signal clk_reconf : std_logic;
signal clk_sys : std_logic;
signal clk_reconf : std_logic;
signal clk_flash : std_logic;
signal clk_scubus : std_logic;
signal rstn_sys : std_logic;
-- RX PLL
signal gxb_locked : std_logic;
......@@ -292,10 +299,6 @@ begin
sfp2_mod1 <= '0' when sfp2_scl_o = '0' else 'Z';
sfp2_mod2 <= '0' when sfp2_sda_o = '0' else 'Z';
Inst_flash_loader_v01 : flash_loader
port map(
noe_in => '0');
dmtd_inst : dmtd_pll port map(
inclk0 => clk_20m_vcxo_i, -- 20 Mhz
c0 => clk_dmtd, -- 62.5MHz
......@@ -308,13 +311,17 @@ begin
sys_inst : sys_pll port map(
inclk0 => clk_125m_local_i, -- 125 Mhz
c0 => clk_pcie, -- 125 MHz
c1 => clk_reconf, -- 50 Mhz
c2 => clk_sys, -- 62.5MHz
c3 => clk_scubus, -- 20 MHz
c4 => open, -- 100 MHz
c0 => clk_62_5, -- 62.5Mhz
c1 => clk_50, -- 50 MHz
c2 => clk_20, -- 20 MHz
locked => sys_locked);
clk_pcie <= clk_ref;
clk_sys <= clk_62_5;
clk_reconf <= clk_50;
clk_flash <= clk_50;
clk_scubus <= clk_20;
sys_reset : gc_reset
generic map(
g_clocks => 1)
......@@ -333,6 +340,22 @@ begin
clks_i(0) => clk_ref,
rstn_o(0) => rstn_ref);
flash : flash_top
generic map(
g_family => "Arria II GX",
g_port_width => 1, -- single-lane SPI bus
g_addr_width => 24, -- 3 byte addressed chip
g_input_latch_edge => '1', -- 30ns at 50MHz (10+20) after falling edge sets up SPI output
g_output_latch_edge => '0', -- falling edge to meet SPI setup times
g_input_to_output_cycles => 2) -- delayed to work-around unconstrained design
port map(
clk_i => clk_sys,
rstn_i => rstn_sys,
slave_i => cbar_master_o(4),
slave_o => cbar_master_i(4),
clk_out_i => clk_flash,
clk_in_i => clk_flash); -- no need to phase shift at 50MHz
rstn_wr <= rstn_sys and gxb_locked;
U_WR_CORE : xwr_core
generic map (
......@@ -601,4 +624,6 @@ begin
hpla_ch(3) <= phy_rx_rbclk;
hpla_ch(4) <= clk_dmtd;
A_SysClock <= clk_scubus;
end rtl;
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